32-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT
Integrated Device Technology, Inc.
IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
IDT49C460E
FEATURES:
• Fast
— IDT49C460E
— IDT49C460D
— IDT49C460C
— IDT49C460B
— IDT49C460A
— IDT49C460
Low-power CMOS
— Commercial: 95mA (max.)
— Military: 125mA (max.)
Improves system memory reliability
— Corrects all single bit errors, detects all double and some
triple-bit errors
Cascadable
— Data words up to 64-bits
Built-in diagnostics
— Capable of verifying proper EDC operation via software
control
Simplified byte operations
— Fast byte writes possible with separate byte enables
Functional replacement for 32- and 64-bit configurations of
the AM29C60 and AM29C660
Available in PGA, PLCC and Fine Pitch Flatpack
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962–88533
Detect
10ns (max.)
12ns (max.)
16ns (max.)
25ns (max.)
30ns (max.)
40ns (max.)
Correct
14ns (max.)
18ns (max.)
24ns (max.)
30ns (max.)
36ns (max.)
49ns (max.)
DESCRIPTION:
The IDT49C460s are high-speed, low-power, 32-bit Error
Detection and Correction Units which generate check bits on
a 32-bit data field according to a modified Hamming Code and
correct the data word when check bits are supplied. The
IDT49C460s are performance-enhanced functional replace-
ments for 32-bit versions of the 2960. When performing a read
operation from memory, the IDT49C460s will correct 100% of
all single bit errors and will detect all double bit errors and
some triple bit errors.
The IDT49C460s are easily cascadable to 64-bits. Thirty-
two-bit systems use 7 check bits and 64-bit systems use 8
check bits. For both configurations, the error syndrome is
made available.
The IDT49C460s incorporate two built-in diagnostic modes.
Both simplify testing by allowing for diagnostic data to be
entered into the device and to execute system diagnostics
functions.
They are fabricated using a CMOS technology designed for
high-performance and high-reliability. The devices are pack-
aged in a 68-pin ceramic PGA, PLCC and Ceramic Quad
Flatpack.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
•
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•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
CB
0–7
DATA
0–31
8
DATA
LATCH
4
8
32
32
DATA
LATCH
CHECK BIT
GENERATE
8
MUX
MUX
CHECK BIT
IN LATCH
LE
IN
13
MUX
DIAGNOSTIC
LATCH
8
5
CONTROL
LOGIC
8
SC
0–7
32
ERROR
CORRECT
ERROR
DECODE
8
MUX
OE
BYTE
0–3
OE
SC
SYNDROME
GENERATE
ERROR
DETECT
ERROR
MULT ERROR
LE
DIAG
LE
OUT
/
GENERATE
CORRECT
CODE ID
1,0
DIAG MODE
1,0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2584 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
AUGUST 1995
DSC-9017/8
11.6
1
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name
DATA
0–31
CB
0–7
LE
IN
I/O
I/O
I
I
Description
32 bidirectional data lines provide input to the Data Input Latch and Diagnostic Latch and also receive output from
the Data Output Latch. DATA
0
is the LSB; DATA
31
is the MSB.
Eight check bit input lines input check bits for error detection and also used to input syndrome bits for error
correction in 64-bit applications.
Latch Enable is for the Data Input Latch. Controls latching of the input data. Data Input Latch and Check Bit Input
Latch are latched to their previous state when LOW. When HIGH, the Data Input Latch and Check Bit Input Latch
follow the input data and input check bits.
A multifunction pin which, when LOW, is in the Check Bit Generate Mode. In this mode, the device generates the
check bits or GENERATE partial check bits specific to the data in the Data Input Latch. The generated check bits
are placed on the SC outputs. Also, when LOW, the Data Out Latch is latched to its previous state.
When HIGH, the device is in the Detect or Correct Mode. In this mode, the device detects single and multiple
errors and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch.
In the Correct Mode, single bit errors are also automatically corrected and the corrected data is placed at the
inputs of the Data Output Latch. The syndrome result is placed on the SC outputs and indicates in a coded form
the number of errors and the specific bit-in-error. When HIGH, the Data Output Latch follows the output of the
Data Input Latch as modified by the correction logic network. In Correct Mode, single bit errors are corrected by
the network before being loaded into the Data Output Latch. In Detect Mode, the contents of the Data Input Latch
are passed through the correction network unchanged into the Data Output Latch. The Data Output Latch is
disabled, with its contents unchanged, if the EDC is in the Generate Mode.
SC
0–7
O
Syndrome Check Bit outputs. Eight outputs which hold the check bits and partial check bits when the EDC is in
the Generate Mode and will hold the syndrome/partial syndrome bits when the device is in the Detect or Correct
modes. All are 3-state outputs.
Output Enable—Syndrome Check Bits. In the HIGH condition, the SC outputs are in the high impedance state.
When LOW, all SC output lines are enabled.
In the Detect or Correct Mode, this output will go LOW if one or more data or check bits contain an error. When
HIGH, no errors have been detected. This pin is forced HIGH in the Generate Mode.
In the Detect or Correct Mode, this output will go LOW if two or more bit errors have been detected. A HIGH level
indicates that either one or no errors have been detected. This pin is forced HIGH in the Generate Mode.
The correct input which, when HIGH, allows the correction network to correct any single-bit error in the Data Input
Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the device will
drive data directly from the Data Input Latch to the Data Output Latch without correction.
Output Enable—Bytes 0, 1, 2, 3. Data Output Latch. Control the three-state output buffers for each of the four
bytes of the Data Output Latch. When LOW, they enable the output buffer of the Data Output Latch. When HIGH,
they force the Data Output Latch buffer into the high impedance mode. One byte of the Data Output Latch is
easily activated by separately selecting the four enable lines.
Select the proper diagnostic mode. They control the initialization, diagnostic and normal operation of the EDC.
These two code identification inputs identify the size of the total data word to be processed. The two allowable
data word sizes are 32 and 64 bits and their respective modified Hamming Codes are designated 32/39 and
64/72. Special CODE ID
1,0
, input 01 is also used to instruct the EDC that the signals CODE ID
1,0
, DIAG MODE
1,0
and CORRECT are to be taken from the Diagnostic Latch rather than from the input control lines.
This is the Latch Enable for the Diagnostic Latch. When HIGH, the Diagnostic Latch follows the 32-bit data on the
input lines. When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic
Latch holds diagnostic check bits and internal control signals for CODE ID
1,0
, DIAG MODE
1,0
and CORRECT.
2584 tbl 01
LE
OUT
/
GENERATE
OE
SC
ERROR
MULT
ERROR
CORRECT
I
O
O
I
OE
BYTE
0–3
I
DIAG
MODE
1,0
CODE ID
1,0
I
I
LE
DIAG
I
11.6
5
FPGA/CPLD
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