NCP6132A, NCP6132B
Product Preview
Dual Output 3 Phase & 2
Phase Controller with
Single SVID Interface for
Desktop and Notebook CPU
Applications
The NCP6132A/NCP6132B dual output three plus two phase buck
solution is optimized for Intel IMVP−7 and VR12 compatible CPUs.
The controller combines true differential voltage sensing, differential
inductor DCR current sensing, input voltage feed−forward, and
adaptive voltage positioning to provide accurately regulated power for
both Desktop and Notebook applications. The control system is based
on Dual−Edge pulse−width modulation (PWM) combined with DCR
current sensing providing the fastest initial response to dynamic load
events and reduced system cost. It also sheds to single phase during
light load operation and can auto frequency scale in light load while
maintaining excellent transient performance.
There are three internal MOSFET drivers inside the chip. One of
these three integrated driver can be configured either to drive core
phase or aux phase. NCP6132A and NCP6132B have almost same
structure except that NCP6132A has two integrated drivers for the
core rail and one integrated driver for auxiliary rail, while the
NCP6132B has all three integrated drivers for the core rail.
Features
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MARKING
DIAGRAM
1
1 60
QFN60
CASE 485BB
x
A
WL
YY
WW
G
NCP6132x
AWLYYWWG
= A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NCP6132AMNR2G
NCP6132BMNR2G
Package
QFN60
(Pb−Free)
Shipping
†
2500/Tape
& Reel
•
Meets Intel’s VR12/IMVP7 Specifications
•
Three Phase CPU Voltage Regulator, and Two Phase Auxiliary
•
•
•
•
•
•
•
•
•
•
•
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Voltage Regulator, with Three Internal MOSFET Drivers in Total
Current Mode Dual Edge Modulation for Fastest Initial Response to
Transient Loading
Dual High Performance Operational Error Amplifier
One Digital Soft Start Ramp for Both Rails
Dynamic Reference Injection
•
Adaptive Voltage Positioning (AVP)
Accurate Total Summing Current Amplifier
•
Vin Feed Forward Ramp Slope
DAC with Droop Feed−forward Injection
•
Pin Programming for Internal SVID Parameters
Dual High Impedance Differential Voltage and Total
•
Over Voltage Protection (OVP) & Under Voltage
Current Sense Amplifiers
Protection (UVP)
Phase−to−Phase Dynamic Current Balancing
•
Over Current Protection (OCP)
“Lossless” DCR Current Sensing for Current Balancing
•
Dual Power Good Output with Internal Delays
Summed Thermally Compensated Inductor Current
•
Pb−free and Halide−free Packages are Available
Sensing for Droop
Applications
True Differential Current Balancing Sense Amplifiers
•
Desktop & Notebook Processors
for Each Phase
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2012
March, 2012
−
Rev. P1
1
Publication Order Number:
NCP6132A/D
NCP6132A, NCP6132B
EN
GND
VCC
VDDBP
TSNS
TSNSA
VRHOT#
SDIO
SCLK
ALERT#
VBOOT
VSP
DAC
GND
VSN
DROOP
CSREF
ENABLE
VSPA
VSNA
DACA
DROOPA
VRDYA
ENABLE
UVLO & EN
AUX VR READY
COMPARATOR
ENABLE
VSP
VSN
DAC
DROOP
VSPA
−
VSNA
VSP
−
VSN
AUX
DAC
GND
VRDY
VR READY
COMPARATOR
VSPA
THERMAL
MONITOR
ENABLE
SVID
INTERFACCE
DATA
REGISTERS
DAC
AUX
DAC
VSPA
VSNA
ADC
MUX
DAC
TSNS
TSNSA
IMON
IMONA
IMAX
IMAXA
AUX
DIFFAMP
VSNA
DROOPA
CSREFA
1.3 V
DIFFA
DIFFAMP
AUX
DAC
−
CSSUMA
CSREFA
CSCOMPA
ILIMA
IOUTA
AUX OVP
OVP
OVPA
IOUTA
ILIMA
1.3 V
DIFF
FB
VSP
VSN
AUX
CS
AMP
+
OVP
−
+
1.3 V
ERROR
AMP
TRBST
DETECT
AUX
ERROR
AMP
TRBSTA
DETECT
−
FBA
+
1.3 V
COMPA
TRBSTA#
CSP1A
COMP
TRBST#
ENABLE
COMP
OVP
ENABLE
CSREF
CSCOMP
ILIM
IOUT
CSREF
CSP1
CSP2
CSP3
+
CSSUM
−
CS
AMP
CORE PHASE
GENERATOR
IOUT
ILIM
AUX
CURRENT
BALANCE
ENABLE
COMPA
OVPA
CSP2A
CSREFA
RAMP1
RAMP2
RAMP3
RAMP
GENERATORS
BSTA
HGA
MAIN
CURRENT
BALANCE
RAMPA2
RAMPA1
AUX
PWM
GENERATOR
SWA
PVCC
LGA
PGND
PWMA
PGND
PVCC
VRMP
PGND
Figure 1. Block Diagram
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2
DRVEN
ROSC
LG1
PVCC
SW1
LG2
BST1
BST2
SW2
HG1
HG2
PWM
NCP6132A, NCP6132B
TRBSTA#
DROOPA
CSCOMPA
CSSUMA
CSREFA
COMPA
TSNSA
46
45
CSP2A
CSP1A
IOUTA
DIFFA
VSNA
VSPA
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
1
60
ILIMA
FBA
PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
NCP6132A/NCP6132B
Tab: GND
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
15
16
FB
COMP
CSCOMP
TRBST#
TSNS
CSP3
CSP1
ILIM
DROOP
CSSUM
DRVEN
CSREF
CSP2
IOUT
31
30
PWM
BST1
Figure 2. QFN60 Pin Diagram
Table 1. QFN60 PIN LIST DESCRIPTION
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Symbol
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
Description
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
Digital Logic power. Connect this pin to VCC with 10
W.
Connect 0.1
mF
capacitor from this pin to
ground
Open drain output. High indicates that the aux output is regulating.
Logic input. Logic high enables both outputs and logic low disables both outputs.
Serial VID data interface.
Serial VID ALERT#.
Serial VID clock.
A resistor to GND on this pin sets the Core and Aux Boot−up Voltage
A resistance from this pin to ground programs the oscillator frequency. This pin supplies a trimmed
output voltage of 2 V.
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to
control of the ramp of PWM slope
Thermal logic output for over temperature.
Open drain output. High indicates that the core output is regulating.
Inverting input to the core differential remote sense amplifier.
Non−inverting input to the core differential remote sense amplifier.
Output of the core differential remote sense amplifier.
Compensation pin for the load transient boost.
Error amplifier voltage feedback for core output
Output of the error amplifier and the inverting inputs of the PWM comparators for the core output.
Total output current monitor for core output. Short it to GND if IMON function is not needed.
Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold.
Used to program droop function for core output. It’s connected to the resistor divider placed between
CSCOMP and CSREF summing node.
Output of total current sense amplifier for core output.
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3
NCP6132A, NCP6132B
Table 1. QFN60 PIN LIST DESCRIPTION
Pin
No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Symbol
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
BST1
HG1
SW1
LG1
PGND
PVCC
LG2
SW2
HG2
BST2
LGA
SWA
HGA
BSTA
PWMA
TSNSA
CSP1A
CSP2A
CSREFA
CSSUMA
CSCOMPA
DROOPA
ILMA
IOUTA
COMPA
FBA
TRBSTA#
DIFFA
VSPA
VSNA
GND
Description
Inverting input of total current sense amplifier for core output.
Total output current sense amplifier reference voltage input. And inverting input to core current bal-
ance sense amplifiers.
Non−inverting input to current balance sense amplifier for phase 3
Non−inverting input to current balance sense amplifier for phase 2
Non−inverting input to current balance sense amplifier for phase 1
Temp Sense input for the core converter.
Bidirectional gate driver enable for external drivers for both core and aux rails. It should be left floating
if unused.
Phase 3 PWM output. A resistor to ground on this pin programs IMAX.
High−Side Bootstrap supply for phase 1
High−Side gate drive output for phase 1
Current return for high−side gate drive for phase 1
Low−Side gate drive output for phase 1
Power ground for gate drivers
Power Supply for gate drivers
Low−Side gate drive output for phase 2
Current return for high−side gate drive for phase 2
High−Side gate drive output for phase 2
High−Side Bootstrap supply for phase 2
Low−Side gate drive output for aux phase 1
Current return for high−side gate drive for aux phase 1
High−Side gate drive output for aux phase 1
High−Side Bootstrap supply for aux phase 1
Aux Phase 2 PWM output. A resistor to ground on this pin programs IMAXA.
Temp sense for the aux converter
Non−inverting input to aux current balance sense amplifier for phase 1
Non−inverting input to aux current balance sense amplifier for phase 2
Total output current sense amplifier reference voltage input for aux. Inverting input to aux current
balance sense amplifier for phase 1 and 2
Inverting input of total current sense amplifier for aux output
Output of total current sense amplifier for aux output
Used to program droop function for aux output. It’s connected to the resistor divider placed between
CSCOMPA and CSREFA.
Over current shutdown threshold setting for aux output. Resistor to CSCOMPA to set threshold.
Total output current monitor for aux output. Short to GND if IMON function is not needed.
Output of aux error amplifier and inverting input of PWM comparator for aux output
Error amplifier voltage feedback for aux output
Compensation pin for load transient boost
Output of the aux differential remote sense amplifier
Non−inverting input to aux differential remote sense amplifier
Inverting input to aux differential remote sense amplifier
Analog ground
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4
NCP6132A, NCP6132B
ABSOLUTE MAXIMUM RATINGS
Table 2. ELECTRICAL INFORMATION
Pin Symbol
COMP, COMPA
CSCOMP, CSCOMPA
VSN, VSNA
DIFF, DIFFA
VRDY, VRDYA
VDDPB, VCC, PVCC
ROSC
IOUT, IOUTA Output
VRMP
SW1, SW2, SWA
BST1, BST2, BSTA
LG1, LG2, LGA
HG1, HG2, HGA
All Other Pins
V
MAX
V
CC
+ 0.3 V
V
CC
+ 0.3 V
GND + 300 mV
V
CC
+ 0.3 V
V
CC
+ 0.3 V
6.5 V
V
CC
+ 0.3 V
TBD
+25 V
28 V
34 V wrt/ GND
6.5 V wrt/ SW
V
CC
+ 0.3 V
BST + 0.3 V
V
CC
+ 0.3 V
V
MIN
−0.3
V
−0.3
V
GND – 300 mV
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−5
V
−10
V
≤
200 ns
−0.3
V wrt/ SW
−0.3
V
−5
V
≤
200 ns
−0.3
V wrt/ SW
−2
V
≤
200 ns wrt/ SW
−0.3
V
I
SOURCE
2 mA
2 mA
1 mA
2 mA
N/A
N/A
1 mA
I
SINK
2 mA
2 mA
1 mA
2 mA
2 mA
N/A
N/A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.
Table 3. THERMAL INFORMATION
Parameters
Thermal Characteristic
QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level
QFN Package
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
T
STG
MSL
Symbol
R
JA
T
J
Typical
31
−10
to +125
−10
to +100
−40
to +150
1
Units
_C/W
_C
_C
_C
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5
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