PD-95291
IRF7807VD2PbF
• Co-Pack N-channel HEXFET Power MOSFET
and Schottky Diode
• Ideal for Synchronous Rectifiers in DC-DC
Converters Up to 5A Output
• Low Conduction Losses
• Low Switching Losses
• Low Vf Schottky Rectifier
• Lead-Free
Description
The FETKY
™
family of Co-Pack HEXFET
®
MOSFETs and
Schottky diodes offers the designer an innovative, board
space saving solution for switching regulator and power
management applications. HEXFET power MOSFETs
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. Combining
this technology with International Rectifier’s low forward
drop Schottky rectifiers results in an extremely efficient
device suitable for use in a wide variety of portable
electronics applications.
The SO-8 has been modified through a customized
leadframe for enhanced thermal characteristics. The SO-
8 package is designed for vapor phase, infrared or wave
soldering techniques.
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain or Source
Current (V
GS
≥
4.5V)
Pulsed Drain Current
Power Dissipation
Schottky and Body Diode
Average ForwardCurrent
25°C
70°C
25°C
70°C
T
J
, T
STG
I
F
(AV)
25°C
70°C
I
DM
P
D
Symbol
V
DS
V
GS
I
D
Max.
30
±20
8.3
6.6
66
2.5
1.6
3.7
2.3
–55 to 150
°C
W
A
A
Units
V
®
FETKY MOSFET / SCHOTTKY DIODE
A/S
A/S
A/S
G
1
8
7
K/D
K/D
K/D
K/D
D
2
3
6
4
5
SO-8
Top View
DEVICE CHARACTERISTICS
IRF7807VD2
R
DS
(on)
Q
G
Q
sw
Q
oss
17mΩ
9.5nC
3.4nC
12nC
Junction & Storage Temperature Range
Thermal Resistance
Parameter
Maximum Junction-to-Ambient
Maximum Junction-to-Lead
R
θJA
R
θJL
Max.
50
20
Units
°C/W
°C/W
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10/08/04
IRF7807VD2PbF
Electrical Characteristics
Parameter
Drain-to-Source
Breakdown Voltage
Static Drain-Source
on Resistance
Gate Threshold Voltage
Drain-Source Leakage
Current
BV
DSS
R
DS(on)
V
GS(th)
I
DSS
1.0
50
6.0
I
GSS
Q
G
Q
GS1
Q
GS2
Q
GD
Q
sw
Q
oss
R
G
t
d (on)
t
r
t
d
t
f
(off)
Min
30
Typ
–
17
Max
–
25
Units
V
m
Ω
V
µA
mA
nA
Conditions
V
GS
= 0V, I
D
= 250µA
V
GS
= 4.5V, I
D
= 7.0A
V
DS
= V
GS
,I
D
= 250µA
V
DS
= 24V, V
GS
= 0
V
DS
= 24V, V
GS
= 0,
Tj = 100°C
V
GS
= ±20V
V
GS
=4.5V, I
D
=7.0A
V
DS
= 16V
Current*
Gate-Source Leakage
Current*
Total Gate Charge*
Pre-Vth
Gate-Source Charge
Post-Vth
Gate-Source Charge
Gate to Drain Charge
Switch Chg(Q
gs2
+ Q
gd
)
Output Charge*
Gate Resistance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
±100
9.5
2.3
1.0
2.4
3.4
12
2.0
6.3
1.2
11
2.2
5.2
16.8
14
nC
V
DS
= 16V, V
GS
= 0
Ω
V
DD
= 16V, I
D
= 7.0A
ns
V
GS
= 5V, R
G
= 2
Ω
Resistive Load
Schottky Diode & Body Diode Ratings and Characteristics
Parameter
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min
V
SD
trr
Qrr
t
on
36
41
Typ
Max
0.54
0.43
Units
Conditions
V T
j
= 25°C, I
s
= 3.0A, V
GS
=0V
T
j
= 125°C, I
s
= 3.0A, V
GS
=0V
ns T
j
= 25°C, I
s
= 7.0A, V
DS
= 16V
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
*
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width
≤
400 µs; duty cycle
≤
2%.
When mounted on 1 inch square copper board
50% Duty Cycle, Rectangular
Typical values of R
DS
(on) measured at V
GS
= 4.5V, Q
G
, Q
SW
and Q
OSS
measured at V
GS
= 5.0V, I
F
= 7.0A.
Device are 100% tested to these parameters.
2
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IRF7807VD2PbF
Power MOSFET Selection for DC/DC
Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on)
of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
4
Drain Current
1
Gate Voltage
t2
V
GTH
t0
t1
t3
Q
GS1
Q
GS2
2
Q
GD
Drain Voltage
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
P
loss
=
(
I
rms
×
R
ds(on )
)
2
Figure 1: Typical MOSFET switching waveform
⎛
Q
⎜
I
×
gd
×
V
in
×
+
i
g
⎝
+
(
Q
g
×
V
g
×
f
)
+
⎛
Q
oss
×
V
in
×
f
⎞
⎝
2
⎠
Q
gs 2
⎞ ⎛
⎞
f
⎟ + ⎜
I
×
×
V
in
×
f
⎟
i
g
⎠ ⎝
⎠
Synchronous FET
The power loss equation for Q2 is approximated
by;
*
P
loss
=
P
conduction
+
P
+
P
output
drive
P
loss
=
I
rms
×
R
ds(on)
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 1.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached (t1) and the time the drain
current rises to I
dmax
(t2) at which time the drain volt-
age begins to change. Minimizing Q
gs2
is a critical fac-
tor in reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure 2 shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
+
(
g
×
V
g
×
f
)
Q
(
2
)
⎛
Q
⎞
+ ⎜
oss
×
V
in
×
f
+
(
Q
rr
×
V
in
×
f
)
⎝
2
⎠
*dissipated primarily in Q1.
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IRF7807VD2PbF
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
Typical Mobile PC Application
The performance of these new devices has been tested
in circuit and correlates well with performance predic-
tions generated by the system models. An advantage of
this new technology platform is that the MOSFETs it
produces are suitable for both control FET and synchro-
nous FET applications. This has been demonstrated with
the 3.3V and 5V converters. (Fig 3 and Fig 4). In these
applications the same MOSFET IRF7807V was used for
both the control FET (Q1) and the synchronous FET
(Q2). This provides a highly effective cost/performance
solution.
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Spice model for IRF7807V can be downloaded in
machine readable format at www.irf.com.
Figure 2: Q
oss
Characteristic
3.3V Supply : Q1=Q2= IRF7807V
93
92
91
Efficiency (%)
5.0V Supply : Q1=Q2= IRF7807V
95
94
93
Efficiency (%)
92
91
90
89
88
Vin=24V
Vin=14V
Vin=10V
90
89
88
87
86
85
84
83
1
2
3
Load current (A)
4
5
Vin=24V
Vin=14V
Vin=10V
87
86
1
2
3
Load current (A)
4
5
Figure 3
Figure 4
4
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IRF7807VD2PbF
RDS(on) , Drain-to -Source On Resistance (
Ω
)
2.0
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
= 7.0A
0.030
1.5
0.025
1.0
0.020
ID = 7.0A
0.015
0.5
0.0
-60 -40 -20
V
GS
= 4.5V
0
20
40
60
80 100 120 140 160
0.010
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
T
J
, Junction Temperature (
°
C)
VGS, Gate -to -Source Voltage (V)
Fig 5.
Normalized On-Resistance
Vs. Temperature
Fig 7.
On-Resistance Vs. Gate Voltage
70
60
VGS
TOP
4.5V
3.5V
3.0V
2.5V
2.0V
BOTTOM 0.0V
70
60
VGS
4.5V
3.5V
3.0V
2.5V
2.0V
BOTTOM 0.0V
TOP
IS, Source-to-Drain Current (A)
50
40
30
20
10
0
0
IS, Source-to-Drain Current (A)
50
40
30
20
10
0
0.0 V
380µs PULSE WIDTH
Tj = 25°C
0.2
0.4
0.6
0.8
1
O.OV
380µS PULSE WIDTH
Tj = 150°C
0
0.2
0.4
0.6
0.8
1
VSD, Source-to-Drain Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig 7.
Typical Reverse Output Characteristics
Fig 8.
Typical Reverse Output Characteristics
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