Micrel, Inc.
3.3V 28Mbps to 1.3Gbps
AnyRate
®
Clock and Data Recovery
SY87701AL
SY87701AL
FEATURES
s
Industrial temperature range (–40
°
C to +85
°
C)
s
3.3V power supply
s
Clock and data recovery from 28Mbps up to 1.3Gbps
NRZ data stream, clock generation from 28Mbps to
1.3Gbps
s
Complies with Bellcore, ITU/CCITT and ANSI
specifications for applications such as OC-1, OC-3,
OC-12, ATM, FDDI, Fibre Channel and Gigabit
Ethernet as well as proprietary applications
s
Two on-chip PLLs: one for clock generation and
another for clock recovery
s
Selectable reference frequencies
s
Differential PECL high-speed serial I/O
s
Line receiver input: no external buffering needed
s
Link fault indication
s
100k ECL compatible I/O
s
Lower power: fully compatible with Micrel's
SY87701V, but with 30% less power
s
Available in 32-pin EPAD-TQFP and 28-pin SOIC
packages (28-pin SOIC is available, but NOT
recommended for new designs.)
DESCRIPTION
The SY87701AL is a complete Clock Recovery and
Data Retiming integrated circuit for data rates from
28Mbps up to 1.3Gbps NRZ. The device is ideally suited
for SONET/SDH/ATM and Fibre Channel applications and
other high-speed data transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
The SY87701AL also includes a link fault detection
circuit.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
APPLICATIONS
s
s
s
s
SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24
Fibre Channel, Escon, SMPTE 259
Gigabit Ethernet/Fast Ethernet
Proprietary architecture up to 1.3Gbps
BLOCK DIAGRAM
PLLR P/N
RDOUTP
(PECL)
RDOUTN
RCLKP
(PECL)
RCLKN
PHASE/
FREQUENCY
DETECTOR
LINK
FAULT
DETECTOR
RDINP
(PECL)
RDINN
PHASE
DETECTOR
0
1
CHARGE
PUMP
VCO
CD
(PECL)
REFCLK
(TTL)
PHASE/
FREQUENCY
DETECTOR
LFIN
(TTL)
CHARGE
PUMP
VCO
1
0
TCLKP
(PECL)
TCLKN
DIVIDER
BY 8, 10, 16, 20
SY87701AL
DIVSEL 1/2
(TTL)
PLLS P/N
FREQSEL 1/2/3
(TTL)
CLKSEL
(TTL)
V
CC
V
CCA
V
CCO
GND
AnyRate is a registered trademark of Micrel, Inc.
M9999-030306
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: March 2006
Micrel, Inc.
SY87701AL
PACKAGE/ORDERING INFORMATION
Ordering Information
VCCA 1
LFIN 2
DIVSEL1 3
RDINP 4
RDINN 5
FREQSEL1 6
REFCLK 7
FREQSEL2 8
FREQSEL3 9
N/C 10
PLLSP 11
PLLSN 12
GNDA 13
GND 14
28 VCC
27 CD
26 DIVSEL2
25 RDOUTP
24 RDOUTN
23 VCCO
22 RCLKP
21 RCLKN
20 VCCO
19 TCLKP
18 TCLKN
17 CLKSEL
16 PLLRP
15 PLLRN
Part Number
SY87701ALZI
SY87701ALHI
SY87701ALZG
SY87701ALHG
(1)
Package
Type
Z28-1
H32-1
Z28-1
H32-1
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY87701ALZI
SY87701ALHI
SY87701ALZG with
Pb-Free bar-line indicator
SY87701ALHG with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
Note:
1. Pb-Free package recommended for new designs.
28-Pin SOIC (Z28-1)
DIVSEL1
LFIN
VCCA
VCCA
VCC
VCC
CD
DIVSEL2
32 31 30 29 28 27 26 25
NC
RDINP
RDINN
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
NC
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
RDOUTP
RDOUTN
VCCO
RCLKP
RCLKN
VCCO
TCLKP
TCLKN
32-Pin EPAD TQFP (H32-1)
M9999-030306
hbwhelp@micrel.com or (408) 955-1690
PLLSP
PLLSN
GNDA
GND
GND
PLLRN
PLLRP
CLKSEL
2
Micrel, Inc.
SY87701AL
PIN DESCRIPTIONS
Pin Number
SOIC
4
5
Pin Number
TQFP
2
3
Pin Name
RDINP
RDINN
Pin Function
Serial Data Input (Differential PECL): These built-in line receiver inputs are
connected to the differential receive serial data stream. An internal receive PLL
recovers the embedded clock (RCLK) and data (RDOUT) information. The
incoming data rate can be within one of eight frequency ranges depending on the
state of the FREQSEL pins. See “Frequency Selection” table.
Reference Clock (TTL Inputs): This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the receiver PLL to keep it
centered in the absence of data coming in on the RDIN inputs.
Carrier Detect (PECL Input): This input controls the recovery function of the
Receive PLL and can be driven by the carrier detect output of optical modules or
from external transition detection circuitry. When this input is HIGH the input data
stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW
the data on the inputs RDIN will be internally forced to a constant LOW, the data
outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW
and the clock recovery PLL forced to look onto the clock frequency generated from
REFCLK.
Frequency Select (TTL Inputs): These inputs select the output clock frequency
range as shown in the “Frequency Selection” table.
Divider Select (TTL Inputs): These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the
“Reference Frequency Selection” table.
Clock Select (TTL Inputs): This input is used to select either the recovered clock
of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer
(CLKSEL = LOW) to the TCLK outputs.
Link Fault Indicator (TTL Output): This output indicates the status of the input data
stream RDIN. Active HIGH signal is indicating when the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH
and RDIN is within the frequency range of the Receive PLL (1000ppm).
Receive Data Output (Differential PECL): These ECL 100k outputs represent the
recovered data from the input data stream (RDIN). This recovered data is specified
against the rising edge of RCLK. These outputs must be terminated with 50Ω to
V
CC
–2 or equivalent. Thhis applies even if these outputs are not used.
Clock Output (Differential PECL): These ECL 100k outputs represent the
recovered clock used to sample the recovered data (RDOUT).
Clock Output (Differential PECL): These ECL 100k outputs represent either the
recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or
the transmit clock of the frequency synthesizer (CLKSEL = LOW). These outputs
must be terminated with 50Ω to V
CC
–2 or equivalent. This applies even if these
outputs are not used.
Clock Synthesis PLL Loop Filter. External loop filter pins for the clock synthesis
PLL.
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL.
Supply Voltage
(1)
Analog Supply Voltage
(1)
Output Supply Voltage
(1)
Ground
No Connect
Analog Ground
7
5
REFCLK
27
26
CD
6
8
9
3
26
17
4
6
7
32
25
16
FREQSEL1
FREQSEL2
FREQSEL3
DIVSEL1
DIVSEL2
CLKSEL
2
31
LFIN
25
24
24
23
RDOUTP
RDOUTN
22
21
19
18
21
20
18
17
RCLKP
RCLKN
TCLKP
TCLKN
11
12
16
15
28
1
20, 23
13, 14
10
13
9
10
15
14
27, 28,
29, 30
19, 22
12, 13
1, 8
11
PLLSP
PLLSN
PLLRP
PLLRN
V
CC
V
CCA
V
CCO
GND
NC
GNDA
Note:
1. V
CC
, V
CCA
, V
CCO
must be the same value.
M9999-030306
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
SY87701AL
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The clock is
phase aligned by a PLL so that it samples the data in the
center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, then PLL will be
declared out of lock, and the PLL will lock to the reference
clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30µs data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY87701AL contains a link fault indication circuit
that monitors the integrity of the serial data input. If the
recovered serial data from RDIN is at the correct data rate
(within 1000ppm of the synthesizer frequency), the Link
Fault Indicator (LFIN) output will be asserted HIGH indicating
an in-lock condition and will remain HIGH as long as this
condition is met.
In the event that the recovered serial data is not at the
correct data rate (greater than 1000ppm difference from the
synthesizer frequency), then LFIN output will go LOW
indicating an out-of-lock condition. This condition will force
the Clock and Data Recovery PLL (CDR) to lock onto the
synthesizer frequency until it is within the correct frequency
range (less than 1000ppm difference from the synthesizer
frequency). Once the CDR is within the correct frequency
range it will again lock onto the RDIN input.
During the interval when the CDR is not locked onto the
RDIN input, the LFIN output will not be a static LOW, but
will be changing.
M9999-030306
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
SY87701AL
CHARACTERISTICS
Performance
The SY87701AL PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the Bellcore
Specifications: GR-253-CORE, Issue 2, December 1995 and
ITU-T Recommendations: G.958 document, when used with
differential inputs and outputs.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak
amplitude of sinusoidal jitter applied on the input signal that
causes an equivalent 1dB optical/electrical power penalty.
SONET input jitter tolerance requirement condition is the
input jitter amplitude which causes an equivalent of 1dB
power penalty.
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter on
the output OC-N/STS-N signal to the jitter applied on the
input OC-N/STS-N signal versus frequency. Jitter transfer
requirements are shown in Figure 2.
Jitter Generation
The jitter of the serial clock and serial data outputs shall
not exceed .01 U.I. rms when a serial data input with no
jitter is presented to the serial data inputs.
A
0.1
Sinusoidal Input
Jitter Amplitude
(UI p-p)
Jitter Transfer (dB)
15
1.5
-20dB/decade
-20dB/decade
-20dB/decade
-20
Acceptable
Range
0.40
f0
f1
f2
Frequency
f4
ft
fc
Frequency
OC/STS-N
Level
3
12
f0
(Hz)
10
10
f1
(Hz)
30
30
f2
(Hz)
300
300
f3
(kHz)
6.5
25
ft
(kHz)
65
250
OC/STS-N
Level
3
12
fc
(kHz)
130
225
P
(dB)
0.1
0.1
Figure 1. Input Jitter Tolerance
Figure 2. Jitter Transfer
M9999-030306
hbwhelp@micrel.com or (408) 955-1690
5
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