SK10/100EP111
Low Voltage 1:10 Differential
LVECL/LVPECL/HSTL Clock Driver
HIGH-PERFORMANCE PRODUCTS
Description
The SK10/100EP111 is a low skew 1-to-10 diffferential
driver, designed with clock distribution in mind. It accepts
two clock sources into an input multiplexer. The LVECL/
LVPECL input signals can be either differential or single-
ended if the VBB output is used. HSTL inputs can be
used when the EP111 is operating under LVPECL
conditions. The selected signal is fanned out to 10
identical differential outputs. The SK10/100EP111 is
fully compatible with MC100EP111 and MC100LVEP111.
The SK10/100EP111 is specifically designed, modeled,
and produced with low skew as the key goal. Optimal
design and layout serve to minimize gate-to-gate skew
within a device, and characterization is used to determine
process control limits that ensure consistent tpd
distributions from lot to lot. The net result is a
dependable, guaranteed low skew device.
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used.
In most applications, all ten differential pairs will be used
and therefore terminated. In the case where fewer than
ten pairs are used, it is necessary to terminate at least
the output pairs on the same package side as the pair(s)
being used on that side in order to maintain minimum
skew. Failure to do this will result in small degradations
of propagation delay (on the order of 10–20 ps) of the
output(s) being used which, while not being catastrophic
to most designs, will mean a loss of skew margin.
The SK10/100EP111, as with most other LVECL devices,
can be operated from a positive VCC supply in LVPECL
mode. This allows the EP111 to be used for high
performance clock distribution in +3.3V or +2.5V
systems. Designers can take advantage of the EP111’s
performance to distribute low skew clocks across the
backplane or the board. In a LVPECL environment, series
or Thevenin line terminations are typically used as they
require no additional power supplies.
Features
•
•
•
•
•
•
•
•
•
•
•
100 ps Part-to-Part Skew
35 ps Output-to-Output Skew
Differential Design
VBB Output
Low Voltage VEE Range of –2.375 to –3.8V for LVECL
Low Voltage VCC Range of +2.375 to +3.8V with
VEE = 0V for LVPECL and HSTL
75 KΩ Internal Input Pulldown Resistors
Fully Compatible with MC100EP111 and
MC100LVEP111
ESD Protection of >4000V
Industrial Temperature Range: –40
o
C to +85
o
C
Available in 32-pin LQFP Package
Functional Block Diagram
CLK0
CLK0*
CLK1
CLK1*
CLK_SEL
10
0
Q0:Q9
1
VBB
Q0*:Q9*
Revision 1/March 2, 2001
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SK10/100EP111
HIGH-PERFORMANCE PRODUCTS
Package Information
A, B
A1,
B1
32
25
4X
0.20 (0.008)
AB
T-U Z
PIN Descriptions
1
24
- T,U,Z -
S, V
S1,V1
8
17
9
16
SEE DETAIL "Y"
SEE DETAIL "AD"
G
- AB -
- AC -
0.10 (0.004) AC
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M,
1982.
2. Controlling Dimension: Millimeter
3. Datum Plane –AB– is located at bottom of lead and
is coincident with the lead where the lead exits the
plastic body at the bottom of the parting line.
4. Datums –T–, –U–, and –Z– to be determined at
Datum Plane –AB–.
5. Dimensions S and V to be determined at Seating
Plane –AC–.
6. Dimensions A and B do not include mold
protrusion. Allowable protrusion is 0.250 (0.010)
per side. Dimensions A and B do not include mold
mismatch and are determined at Datum Plane –AB–.
7. Dimension D does not include Dambar protrusion.
Dambar protrusion shall not cause the D dimension
to exceed 0.520 (0.020).
8. Minimum solder plate thickness shall be
0.0075 (0.0003).
9. Exact shape of each corner may vary
from depiction.
MILLIMETERS
DI M
A
MIN
MAX
I NCHE S
MIN
MAX
7. 000 BSC
3. 500 BSC
7. 000 BSC
3. 500 BSC
1. 400
0. 300
1. 350
0. 300
1. 600
0. 450
1. 450
0. 400
0. 276 BSC
0. 138 BSC
0. 276 BSC
0. 138 BSC
0. 055
0. 012
0. 053
0. 012
0. 063
0. 018
0. 057
0. 016
8x M
˚
A1
R
B
B1
C
E
C
D
E
W
H
X
K
Q
˚
0.250 (0.010)
GAUGE PLANE
.
G
H
0. 800 BSC
0. 050
0. 090
0. 500
0. 150
0. 200
0. 700
0. 031 BSC
0. 002
0. 004
0. 020
0. 006
0. 008
0. 028
DETAIL AD
J
K
M
Base Metal
12
o
RE .
0. 090
0. 160
12
o
RE.
0. 004
0. 006
N
P
Q
N
0. 400 BSC
1
o
0. 150
5
o
0. 250
0. 016 BSC
1
o
0. 006
5
o
0. 010
–T–, –Ü–, –Z–
R
F
AE
P
D
S
S1
9. 000 BSC
4. 500 BSC
9. 000 BSC
4. 500 BSC
0. 200 RE.
1. 000 RE.
0. 354 BSC
0. 177 BSC
0. 354 BSC
0. 177 BSC
0. 008 RE.
0. 039 RE.
N
AE
V
M AC T –U
Z
0.20 (0.008)
V1
W
DETAIL Y
Revision 1/March 2, 2001
SECTION AE
3
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SK10/100EP111
HIGH-PERFORMANCE PRODUCTS
DC Characteristics (continued)
SK10/100EP111 HSTL DC Electrical Characteristics
(V
CC
– V
EE
= +2.375V to +3.8V; V
CC
= V
CCO
; VOUT Loaded 50Ω to V
CC
– 2.0V)
Ω
TA = –40
o
C
S y mb o l
V
C MR
V
PP
Ch a r a c t e r i s t i c
C o mmo n Mo d e R a n g e
2
Mi n i mu m I n p u t S w i n g
Mi n
VEE +
0. 9
500
Typ
Ma x
VCC -
1. 1
Mi n
VEE +
0. 9
500
TA = 0
o
C
Typ
Ma x
VCC -
1. 1
TA = +25
o
C
Mi n
VEE +
0. 9
500
Typ
Ma x
VCC -
1. 1
TA = +85
o
C
Mi n
VEE +
0. 9
500
Typ
Ma x
VCC -
1. 1
Un i t
V
mV
AC Characteristics
SK10/100EP111 AC Electrical Characteristics
(V
CC
– V
EE
= +2.375V to +3.8V; V
CC
= V
CCO
; VOUT Loaded 50Ω to V
CC
– 2.0V)
Ω
TA = –40
o
C
Symbol
f
ma x
t
PLH
t
P HL
t
P HL
t
PLH
t
pd
t
skew
V
C MR
t
r
, t
f
Ch a r a c t e r i s t i c
Max Input .requency
ECL/PECL Pr op
Delay to Output
HST L P r o p
Delay to Output
Propagation Delay
EN t o Q
Within-Device Skew
Par t-to-Par t Skew
C o mmo n Mo d e R a n g e
3
Output Rise/.all Time
( 2 0 % t o 8 0 %)
VEE +
1. 7
175
220
400
550
930
Min
Typ
1500
430
580
1100
15
100
460
620
1360
30
145
VCC -
0. 3
500
VEE +
1. 7
180
410
585
930
Max
Min
TA = 0
o
C
Typ
1500
450
620
1100
15
100
535
690
1360
30
130
VCC -
0. 3
230
450
VEE +
1. 7
180
420
610
930
Max
Min
TA = +25
o
C
Typ
1500
455
640
1100
15
100
545
720
1360
30
135
VCC -
0. 3
245
450
Max
TA = +85
o
C
Min
Typ
1500
440
640
930
480
670
1100
15
100
VEE +
1. 7
190
260
545
750
1360
30
150
VCC -
0. 3
385
Max
Un i t
MH z
ps
ps
ps
ps
ps
V
ps
Notes:
1.
These values are for V
CC
= 3.3V. Level Specifications will vary 1:1 with V
CC
.
2.
CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP
(min)
and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.7V.
3.
For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data Sheet.
4.
For part ordering description, see HPP Part Ordering Information Data Sheet.
Revision 1/March 2, 2001
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