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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
D
D
D
D
D
D
D
D
D
D
10-Bit Resolution, 30 MSPS
Analog-to-Digital Converter
Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital
Clamp
– Differential
Built-In Programmable Gain Amplifier
(PGA)
Differential Nonlinearity:
±
0.3 LSB
Signal-to-Noise: 56 dB
Spurious Free Dynamic Range: 60 dB
Adjustable Internal Voltage Reference
Straight Binary/2s Complement Output
Out-of-Range Indicator
Power-Down Mode
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
AGND
DV
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
OVR
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
AIN
VREF
REFBS
REFBF
MODE
REFTF
REFTS
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK
description
The THS1031 is a CMOS, low-power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 3 V to 5.5 V. The THS1031 has been designed to give circuit developers flexibility. The
analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp amplifier
whose clamp input level can be driven from an external dc source or from an internal high-precision 10-bit digital
clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR for small
signals. The THS1031 provides a wide selection of voltage references to match the user’s design requirements.
For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the application. The out-of-range output indicates any
out-of-range condition in THS1031’s input signal. The format of digital output can be coded in either unsigned
binary or 2s complement.
The speed, resolution, and single-supply operation of the THS1031 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allows dc restoration of video signal and is suitable for video applications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both
imaging and communications systems.
The THS1031C is characterized for operation from 0°C to 70°C, while the THS1031I is characterized for
operation from –40°C to 85°C.
AVAILABLE OPTIONS
TA
0°C to 70°C
– 40°C to 85°C
PACKAGED DEVICES
28-TSSOP (PW)
THS1031CPW
THS1031IPW
28-SOIC (DW)
THS1031CDW
THS1031IDW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
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•
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1
THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
functional block diagram
Power Down
10-Bit
Clamp
10
CLAMPIN
CLAMP
DAC
Control
Register
WR
Clamp
Amplifier
3
10
Core
PGA
DAC
ADC
Output
Buffer
I/O(0–9)
AIN
REFTS
REFBS
A
Sample
and
Hold
Internal
Reference
B
Buffer
OVR
OE
MODE
REFTF
REFBF
Timing
Circuit
VBG
ORG
GND
REFSENSE
VREF
CLK
2
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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
Terminal Functions
TERMINAL
NAME
AGND
AIN
AVDD
CLAMP
CLAMPIN
CLK
DGND
DVDD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
MODE
OE
OVR
REFBS
REFBF
REFSENSE
REFTF
REFTS
VREF
WR
NO.
1
27
28
19
20
15
14
2
3
4
5
6
7
8
9
10
11
12
23
16
13
25
24
18
22
21
26
17
I/O
I
I
I
I
I
I
I
I
Analog ground
Analog input
Analog supply
High to enable clamp mode, low to disable clamp mode
Connect to an external analog clamp reference input.
Clock input
Digital ground
Digital driver supply
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
Mode input
High to 3-state the data bus, low to enable the data bus
Out-of-range indicator
Reference bottom sense
Reference bottom decoupling
Reference sense
Reference top decoupling
Reference top sense
Internal and external reference
Write strobe
DESCRIPTION
I/O
I
I
O
I
I
I
I
I
I/O
I
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3
THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range: AV
DD
to AGND, DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 0.3 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 6.5 V to 6.5 V
Mode input voltage range, MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AV
DD
+ 0.3 V
Reference voltage input range, REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . – 0.3 V to AV
DD
+ 0.3 V
Analog input voltage range, AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AV
DD
+ 0.3 V
Reference input voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AV
DD
+ 0.3 V
Reference output voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AV
DD
+ 0.3 V
Clock input voltage range, CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AV
DD
+ 0.3 V
Digital input voltage range, digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DV
DD
+ 0.3 V
Digital output voltage range, digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DV
DD
+ 0.3 V
Operating junction temperature range, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
digital inputs
MIN
High-level
High level input voltage VIH
voltage,
Low-level in ut voltage VIL
input voltage,
Clock input
All other inputs
Clock input
All other inputs
0.8
×
AVDD
0.8
×
DVDD
0.2
×
AVDD
0.2
×
DVDD
NOM
MAX
UNIT
V
V
analog inputs
MIN
Analog input voltage, VI(AIN) (PGA = 1x, top, bottom, or external reference mode)
Reference input voltage, VI(VREF)
Clamp input voltage, VI(CLAMPIN)
REFBS
1
0.1
NOM
MAX
REFTS
2
AVDD–0.1
UNIT
V
V
V
power supply
MIN
Supply voltage
Maximum sampling rate = 30 MSPS
AVDD
DVDD
3
3
NOM
3.3
3.3
MAX
5.5
5.5
UNIT
V
REFTS, REFBS reference voltages (MODE = AV
DD
)
PARAMETER
REFTS
REFBS
Reference input voltage (top)
Reference input voltage (bottom)
Differential input voltage (REFTS – REFBS)
Switched input capacitance on REFTS or REFBS
MIN
1
0
1
0.6
NOM
MAX
AVDD
AVDD–1
2
UNIT
V
V
V
pF
sampling rate and resolution
PARAMETER
fs
Sample frequency
Resolution
MIN
5
10
NOM
MAX
30
UNIT
MHz
Bits
4
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