74AHC00-Q100;
74AHCT00-Q100
Quad 2-input NAND gate
Rev. 1 — 16 April 2013
Product data sheet
1. General description
The 74AHC00-Q100; 74AHCT00-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. JESD7-A.
The 74AHC00-Q100; 74AHCT00-Q100 provides the quad 2-input NAND function.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC00-Q100: CMOS level
For 74AHCT00-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74AHC00-Q100; 74AHCT00-Q100
Quad 2-input NAND gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC00-Q100
74AHC00D-Q100
74AHC00PW-Q100
74AHC00BQ-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO14
TSSOP14
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT402-1
Name
Description
Version
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
SO14
TSSOP14
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT402-1
74AHCT00-Q100
74AHCT00D-Q100
40 C
to +125
C
74AHCT00PW-Q100
40 C
to +125
C
74AHCT00BQ-Q100
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2
4
2Y 6
5
9
10
12
13
mna212
&
3
&
6
3Y 8
&
8
A
4Y 11
&
mna246
11
B
Y
mna211
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
74AHC_AHCT00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
2 of 15
NXP Semiconductors
74AHC00-Q100; 74AHCT00-Q100
Quad 2-input NAND gate
5. Pinning information
5.1 Pinning
$+&4
$+&74
WHUPLQDO
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9
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*1'
%
*1'
<
$
DDD
$+&4
$+&74
$
%
<
$
%
<
*1'
DDD
9
&&
%
$
<
%
$
<
%
<
$
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<
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
74AHC_AHCT00_Q100
All information provided in this document is subject to legal disclaimers.
$
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
3 of 15
NXP Semiconductors
74AHC00-Q100; 74AHCT00-Q100
Quad 2-input NAND gate
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function selection
[1]
Output
nB
X
L
H
nY
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<0.5 V or V
O
> V
CC
+ 0.5 V
V
O
=0.5 V to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
74AHC00-Q100
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
2.0
0
0
40
-
-
5.0
-
-
+25
-
-
5.5
5.5
V
CC
+125
100
20
V
V
V
C
ns/V
ns/V
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
74AHC_AHCT00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
4 of 15
NXP Semiconductors
74AHC00-Q100; 74AHCT00-Q100
Quad 2-input NAND gate
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Operating conditions
…continued
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 4.5 V to 5.5 V
Conditions
Min
4.5
0
0
40
-
Typ
5.0
-
-
+25
-
Max
5.5
5.5
V
CC
+125
20
Unit
V
V
V
C
ns/V
74AHCT00-Q100
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74AHC00-Q100
V
IH
HIGH-level input
voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level input
voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
I
O
=
4.0
mA; V
CC
= 3.0 V
I
O
=
8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level output V
I
= V
IH
or V
IL
voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
supply current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3.0
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
1.9
2.9
4.4
2.48
3.80
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
A
A
pF
1.5
2.1
3.85
-
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
1.5
2.1
3.85
-
-
-
-
-
-
0.5
0.9
1.65
1.5
2.1
3.85
-
-
-
-
-
-
0.5
0.9
1.65
V
V
V
V
V
V
Conditions
Min
25
C
Typ Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
input capacitance V
I
= V
CC
or GND
74AHC_AHCT00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
5 of 15
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