HCPL-7860/786J
HCPL-0870/7870
Isolated 15-bit A/D Converter
Data Sheet
Features
• 12-bit linearity
• 800 ns conversion time (pre-trigger
mode 2)
• 5 conversion modes for resolution/
speed trade-off:
12-bit effective resolution with 20
µs
signal delay (14-bit with 103
µs)
• Fast 3
µs
over-range detection
• Serial I/O (SPI
®
, QSPI
®
and
Microwire
®
compatible)
•
±
200 mV input range with single
5 V supply
• 1% internal reference voltage
matching
• Offset calibration
• -40°C to +85°C operating
temperature range
• 15 kV/µs isolation transient
immunity
• Regulatory approvals:
UL, CSA, IEC/EN/DIN EN 60747-5-2
DIGITAL CURRENT SENSOR
+
ISOLATION
BOUNDARY
+
HCPL-7860/
HCPL-786J
INPUT
CURRENT
ISOLATED
MODULATOR
DIGITAL
INTERFACE IC
Avago’s Isolated A/D Converter delivers the reliability, small size, superior isolation and over-temperature
performance motor drive designers need to
accurately measure current at half the price of traditional
solutions.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Inc.
HCPL-x870
OUTPUT
DATA
MICRO-CONTROLLER
Digital Current Sensing Circuit
As shown in Figure 1, using the
Isolated 2-chip A/D converter to
sense current can be as simple
as connecting a current-sensing
resistor, or shunt, to the input
and reading output data through
the 3-wire serial output
interface. By choosing the
appropriate shunt resistance,
any range of current can be
monitored, from less than 1 A to
more than 100 A.
Even better performance can be
achieved by fully utilizing the
more advanced features of the
Isolated A/D converter, such as
the pre-trigger circuit which can
reduce conversion time to less
NON-ISOLATED
+5V
than 1
µs,
the fast over-range
detector for quickly detecting
short circuits, different
conversion modes giving various
resolution/speed trade-offs,
offset calibration mode to
eliminate initial offset from
measurements, and an
adjustable threshold detector for
detecting non-short circuit
overload conditions.
ISOLATED
+5V
INPUT
CURRENT R
SHUNT
0.02
CCLK
CLAT
V
DD
CHAN
SCLK
SDAT
CS
THR1
OVR1
RESET
3-WIRE
SERIAL
INTERFACE
+
C1
0.1 µF
V
DD1
V
IN+
V
IN-
GND1
V
DD2
MCLK
MDAT
GND2
CDAT
MCLK1
MDAT1
MCLK2
MDAT2
GND
C2
0.1 µF
+
C3
10 µF
HCPL-7860/
HCPL-786J
HCPL-x870
Figure 1: Typical application circuit.
Product Overview
Description
The HCPL-7860/HCPL-786J
Isolated Modulator and the HCPL-
x870 Digital Interface IC together
form an isolated programmable
two-chip analog-to-digital
converter. The isolated modulator
allows direct measurement of
motor phase currents in power
inverters while the digital
interface IC can be programmed
to optimize the conversion speed
and resolution trade-off.
In operation, the HCPL-7860/
HCPL-786J Isolated Modulator
(optocoupler with 3750 V
RMS
dielectric withstand voltage
rating) converts a low-bandwidth
analog input into a high-speed
one-bit data stream by means of a
sigma-delta (
∑
∆)
oversampling
modulator. This modulation
provides for high noise margins
and excellent immunity against
isolation-mode transients. The
modulator data and on-chip
sampling clock are encoded and
transmitted across the isolation
boundary where they are
recovered and decoded into
separate high-speed clock and
data channels.
The Digital Interface IC converts
the single-bit data stream from
the Isolated Modulator into
fifteen-bit output words and
provides a serial output interface
that is compatible with SPI
®
,
QSPI
®
, and Microwire
®
protocols,
allowing direct connection to a
microcontroller. The Digital
Interface IC is available in two
package styles: the HCPL-7870 is
in a 16-pin DIP package and the
HCPL-0870 is in a 300-mil wide
SO-16 surface-mount package.
Features of the Digital Interface
IC include five different conver-
sion modes, three different pre-
trigger modes, offset calibration,
fast over-range detection, and
adjustable threshold detection.
Programmable features are con-
figured via the Serial Configura-
tion port. A second multiplexed
input is available to allow
measurements with a second
isolated modulator without
additional hardware. Because the
two inputs are multiplexed, only
one conversion at a time can be
made and not all features are
available for the second channel.
The available features for both
channels are shown in the table at
right.
2
HCPL-x870 Digital Interface IC
Feature
Conversion Mode
Offset Calibration
Pre-Trigger Mode
Over-Range Detection
Adjustable Threshold Detection
Channel #1
✓
✓
✓
✓
✓
Channel #2
✓
✓
Functional Diagrams
ISOLATION
BOUNDARY
V
DD1
V
IN+
1
2
3
4
5
6
7
8
SIGMA-
DELTA
MOD./
ENCODER
DECODER
16 GND2
15 NC
CCLK
CLAT
CDAT
MCLK1
MDAT1
MCLK2
MDAT2
GND
1
2
3
4
CH1
CONFIG.
INTER-
FACE
CON-
VERSION
INTER-
FACE
16 V
DD
15 CHAN
V
DD1
V
IN+
V
IN–
GND1
1
2
3
4
8
7
DECODE
V
DD2
MCLK
MDAT
GND2
V
IN–
NC
NC
14
V
DD2
13
MCLK
12 NC
11 MDAT
14
SCLK
13
SDAT
12 CS
SIGMA-
DELTA
MOD./
ENCODE
5
6
7
8
CH2
THRES-
HOLD
DETECT
&
RESET
6
5
NC
NC
11 THR1
10
NC
9
GND2
10
OVR1
9
RESET
SHIELD
GND1
HCPL-7860 Isolated
Modulator
HCPL-786J Isolated
Modulator
HCPL-x870 Digital
Interface IC
Pin Description, Isolated Modulator
Symbol
V
DD1
V
IN+
V
IN–
GND1
Description
Supply voltage input (4.5 V to 5.5 V)
Positive input (±200 mV
recommended)
Negative input
(normally connected to GND1)
Input ground
Symbol
V
DD2
MCLK
MDAT
GND2
Description
Supply voltage input (4.5 V to 5.5 V)
Clock output (10 MHz typical)
Serial data output
Output ground
3
Pin Description, Digital Interface IC
Symbol
CCLK
Description
Clock input for the Serial Configuration
Interface (SCI). Serial Configuration
data is clocked in on the rising edge
of CCLK.
Latch input for the Serial Configuration
Interface (SCI). The last 8 data bits
clocked in on CDAT by CCLK are
latched into the appropriate
configuration register on the rising
edge of CLAT.
Data input for the Serial Configuration
Interface (SCI). Serial configuration
data is clocked in MSB first.
Channel 1 Isolated Modulator clock
input. Input Data on MDAT1 is clocked
in on the rising edge of MCLK1.
Symbol
V
DD
Description
Supply voltage (4.5 V to 5.5 V).
CLAT
CHAN
Channel select input. The input level on
CHAN determines which channel of
data is used during the next conversion
cycle. An input low selects channel 1,
a high selects channel 2.
Serial clock input. Serial data is clocked
out of SDAT on the falling edge of SCLK.
Serial data output. SDAT changes from
high impedance to a logic low output
at the start of a conversion cycle.
SDAT then goes high to indicate that
data is ready to be clocked out. SDAT
returns to a high-impedance state after
all data has been clocked out and CS
has been brought high.
Conversion start input. Conversion
begins on the falling edge of CS. CS
should remain low during the entire
conversion cycle and then be brought
high to conclude the cycle.
Continuous, programmable-threshold
detection for channel 1 input data. A
high level output on THR1 indicates
that the magnitude of the channel 1
input signal is beyond a user
programmable threshold level between
160 mV and 310 mV. This signal
continuously monitors channel 1
independent of the channel select
(CHAN) signal.
High speed continuous over-range
detection for channel 1 input data. A
high level output on OVR1 indicates
that the magnitude of the channel 1
input is beyond full-scale. This signal
continuously monitors channel 1
independent of the CHAN signal.
Master reset input. A logic high input
for at least 100 ns asynchronously
resets all configuration registers to
their default values and zeroes the
Offset Calibration registers.
CDAT
SCLK
MCLK1
SDAT
MDAT1
Channel 1 Isolated Modulator data
input.
CS
MCLK2
Channel 2 Isolated Modulator clock
input. Input Data on MDAT2 is clocked
in on the rising edge of MCLK2.
THR1
MDAT2
Channel 2 Isolated Modulator data
input.
OVR1
GND
Digital ground.
RESET
4
Isolated A/D Converter Performance
Electrical Specifications
Unless otherwise noted, all specifications are at V
IN+
= -200 mV to +200 mV and V
IN-
= 0 V; all Typical specifications are at
T
A
= 25°C and V
DD1
= V
DD2
= V
DD
= 5 V; all Minimum/Maximum specifications are at T
A
= -40°C to +85°C,
V
DD1
= V
DD2
= V
DD
= 4.5 to 5.5 V.
Parameter
Symbol
STATIC CONVERTER CHARACTERISTICS
Resolution
Integral Nonlinearity
INL
Min.
15
3
0.01
0
2
0.12
320
30
0.14
1
3
10
Typ.
Max.
Units
bits
LSB
%
LSB
mV
µV/ °C
mV/V
mV
%
%
ppm/°C
%
mV
Test Conditions
Fig. Note
1
2
3
V
IN+
= 0 V
5
4
3
4
Differential Nonlinearity
DNL
Uncalibrated Input Offset
V
OS
-3
Offset Drift vs. Temperature
dV
OS
/dT
A
Offset drift vs. V
DD1
dV
OS
/dV
DD1
Internal Reference Voltage
V
REF
Absolute Reference Voltage
-4
Tolerance
Reference Voltage
-2
Matching
V
REF
Drift vs. Temperature
dV
REF
/dT
A
V
REF
Drift vs. V
DD1
dV
REF
/dV
DD1
Full Scale Input Range
-V
REF
Recommended Input
-200
Voltage Range
DYNAMIC CONVERTER CHARACTERISTICS
(Digital Interface IC is set to Conversion Mode 3.)
Signal-to-Noise Ratio
SNR
62
Total Harmonic Distortion
THD
Signal-to-(Noise
SND
+ Distortion)
Effective Number of Bits
ENOB
10
Conversion Time
t
C2
t
C1
t
C0
Signal Delay
t
DSIG
Over-Range Detect Time
t
OVR1
2.0
Threshold Detect Time
t
THR1
Signal Bandwidth
BW
18
Isolation Transient
CMR
15
Immunity
4
2
60
0.2
+V
REF
+200
6
T
A
= 25°C.
See Note 5
5
73
-67
66
12
0.8
20
40
20
3.0
10
22
20
dB
V
IN+
= 35 Hz,
400 mV
pk-pk
(141 mV
rms
) sine
wave.
Pre-Trigger Mode 2
Pre-Trigger Mode 1
Pre-Trigger Mode 0
V
IN+
= 0 to 400 mV
step waveform
2,9
1.1
24
48
24
4.2
bits
µs
8
7,
14
10
12
11
6
7
kHz
kV/µs
V
ISO
= 1 kV
8
9
10
11
12
5
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