LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-
HSTL FANOUT BUFFER
ICS85214
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Five differential HSTL compatible outputs
Selectable differential CLK0, CLK0 or LVCMOS/LVTTL clock
inputs
CLK0, CLK0 pair can accept the following differential input
levels: LVPECL, LVDS, HSTL, HCSL, SSTL
CLK1 can accept the following input levels: LVCMOS or LVTTL
Output frequency up to: 700MHz
Translates any single-ended input signal to HSTL levels with
resistor bias on CLK0 input
Output skew: 30ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.8ns (maximum)
3.3V core, 1.8V output operating supply
0°C to 85°C ambient operating temperature
Industrial temperature information available upon request
Available in lead-free (RoHS 6) package
For functional replacement part use 8523
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
The ICS85214 is a low skew, high performance
1-to-5 Differential-to-HSTL Fanout Buffer and a
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The CLK0,
CLK0 pair can accept most standard differential
input levels. The single ended CLK1 input accepts LVCMOS or
LVTTL input levels. Guaranteed output and part-to-part skew
characteristics make the ICS85214 ideal for those clock distri-
bution applications demanding well defined performance and
repeatability.
ICS
Block Diagram
CLK_EN
Pulldown
D
Q
CLK0
Pullup
CLK0
Pulldown
CLK1
Pulldown
CLK_SEL
Pulldown
LE
0
0
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Pin Assignment
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
CLK_EN
V
DD
nc
CLK1
CLK0
CLK0
nc
CLK_SEL
GND
1
1
ICS85214
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
IDT™ / ICS™
HSTL FANOUT BUFFER
1
ICS85214AG
REV. B
JUNE 3, 2016
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11
12
13, 17
14
15
16
18
19
20
Name
Q0, Q0
Q1, Q1
Q2, Q2
Q3, Q3
Q4, Q4
GND
CLK_SEL
nc
CLK0
CLK0
CLK1
V
DD
CLK_EN
V
DDO
Output
Output
Output
Output
Output
Power
Input
Unused
Input
Input
Input
Power
Input
Power
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Type
Description
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
Clock select input. When HIGH, selects differential CLK1input. When LOW,
selects CLK0, CLK0 inputs. LVCMOS/LVTTL interface levels.
No connect.
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Positive supply pin.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
When HIGH, Qx outputs are forced low, Qx outputs are forced high.
LVTTL/LVCMOS interface levels.
Output supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
IDT™ / ICS™
HSTL FANOUT BUFFER
2
ICS85214AG
REV. B
JUNE 3, 2016
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
CLK_EN
0
1
Q0:Q4
Enabled
Disabled; LOW
Outputs
Q0:Q4
Enabled
Disabled; HIGH
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, CLK0 inputs as described in Table 3B.
Disabled
CLK0
CLK0
Enabled
CLK_EN
Q0:Q4
Q0:Q4
Figure 1.
CLK_EN
Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK0 or CLK1
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
CLK0
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q[0:4]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
Q[0:4]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section,
Wiring the Differential Input to Accept Single-Ended Levels.
IDT™ / ICS™
HSTL FANOUT BUFFER
3
ICS85214AG
REV. B
JUNE 3, 2016
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
DDO
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
73.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
80
Units
V
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK1,
CLK_EN, CLK_SEL
CLK1,
CLK_EN, CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 85°C
Symbol
I
IH
Parameter
CLK
Input High Current
CLK
CLK
I
IL
V
PP
V
CMR
Input Low Current
CLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
IDT™ / ICS™
HSTL FANOUT BUFFER
4
ICS85214AG
REV. B
JUNE 3, 2016
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Table 4D. HSTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 85°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Current;
NOTE 1
Output Low Current;
NOTE 1
Output
Crossover Voltage
Peak-to-Peak
Output Voltage Swing
Test Conditions
Minimum
1.0
0
38% x (V
OH
– V
OL
) + V
OL
0.6
Typical
Maximum
1.4
0.4
60% x (V
OH
– V
OL
) + V
OL
1.1
Units
V
V
V
V
NOTE 1: Outputs termination with 50 to ground.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 85°C
Parameter Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Output Frequency
CLK0, CLK0
CLK1
ƒ
700MHz
1.0
Test Conditions
Minimum
Typical
Maximum
700
300
1.8
30
250
20% to 80%
200
46
45
700
54
55
Units
MHz
MHz
ns
ps
ps
ps
%
%
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
CLK0, CLK0
CLK1
All parameters measured at
fMAX
unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from either the differential input crossing point or VDD/2 to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.Parameter Measurement Information
IDT™ / ICS™
HSTL FANOUT BUFFER
5
ICS85214AG
REV. B
JUNE 3, 2016
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
