INTEGRATED CIRCUITS
DATA SHEET
TZA3019
2.5 Gbits/s dual
postamplifier with level
detectors and 2
×
2 switch
Preliminary specification
File under Integrated Circuits, IC19
2000 Apr 10
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level
detectors and 2
×
2 switch
FEATURES
•
Dual postamplifier
•
Single 3.3 V power supply
•
Wideband operation from 50 kHz to 2.5 GHz (typical
value)
•
Fully differential
•
Channels are delay matched
•
On-chip DC-offset compensations without external
capacitor
•
Interfacing with positive or negative supplied logic
•
Switching possibility between channels
•
Positive Emitter Coupled Logic (PECL) or Current-Mode
Logic (CML) compatible data outputs adjustable from
200 to 800 mV (p-p) single-ended
•
Power-down capability for unused outputs and detectors
•
Rise and fall times 80 ps (typical value)
•
Possibility to invert the output of each channel
separately
•
Input level-detection circuits for Received Signal
Strength Indicator (RSSI) or Loss Of Signal (LOS)
detection, programmable from 0.4 to 400 mV (p-p)
single-ended, with open-drain comparator output for
direct interfacing with positive or negative logic
•
Reference voltage for output level and LOS adjustment
•
Automatic strongest input signal switch possibility
(TZA3019 version B)
•
HTQFP32 or HBCC32 plastic package with exposed
pad.
APPLICATIONS
TZA3019
•
Postamplifier for Synchronous Digital Hierarchy and
Synchronous Optical Network (SDH/SONET)
transponder
•
SDH/SONET wavelength converter
•
Crosspoint or channel switch
•
PECL driver
•
Fibre channel arbitrated loop
•
Protection ring
•
Monitoring
•
Signal level detectors
•
Swing converter CML 200 mV (p-p) to
PECL 800 mV (p-p)
•
Port bypass circuit
•
2.5 GHz clock amplification.
GENERAL DESCRIPTION
The TZA3019 is a low gain postamplifier multiplexer with a
dual RSSI and/or LOS detector that is designed for use in
critical signal path control applications, such as
loop-through, redundant channel switching or Wavelength
Division Multiplexing (WDM). The signal path is
unregistered, so no clock is required for the data inputs.
The signal path is fully differential and delay matched. It is
capable of operating from 50 kHz to 2.5 GHz.
The TZA3019 HTQFP32 and HBCC32 packages can be
delivered in three versions:
•
TZA3019AHT and TZA3019AV with two RSSI signals
•
TZA3019BHT and TZA3019BV with one RSSI and one
LOS signal
•
TZA3019CHT and TZA3019CV with two LOS signals.
ORDERING INFORMATION
TYPE
NUMBER
TZA3019AHT
TZA3019BHT
TZA3019CHT
TZA3019AV
TZA3019BV
TZA3019CV
TZA3019U
PACKAGE
NAME
HTQFP32
HTQFP32
HTQFP32
HBCC32
HBCC32
HBCC32
−
DESCRIPTION
plastic, heatsink thin quad flat package; 32 leads; body 5
×
5
×
1 mm
plastic, heatsink thin quad flat package; 32 leads; body 5
×
5
×
1 mm
plastic, heatsink thin quad flat package; 32 leads; body 5
×
5
×
1 mm
plastic, heatsink bottom chip carrier; 32 terminals; body 5
×
5
×
0.65 mm
plastic, heatsink bottom chip carrier; 32 terminals; body 5
×
5
×
0.65 mm
plastic, heatsink bottom chip carrier; 32 terminals; body 5
×
5
×
0.65 mm
bare die; 2.22
×
2.22
×
0.28 mm
VERSION
SOT547-2
SOT547-2
SOT547-2
SOT560-1
SOT560-1
SOT560-1
−
2000 Apr 10
2
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level
detectors and 2
×
2 switch
BLOCK DIAGRAM
TZA3019
handbook, full pagewidth
VEE1A
LOSTH1
32
10
25
VEE1B
LOS
DETECTOR
1×
offset
27
RSSI1
LEVEL1
INV1
S1
GND1A
IN1
IN1Q
GND1A
12
29
31
1
2
3
4
TZA3019AHT
TZA3019AV
level
24
SWITCH
23
22
A1A
A1B
21
GND1B
OUT1
OUT1Q
GND1B
TEST
15
DFT
BAND GAP
REFERENCE
14
Vref
GND2A
IN2Q
IN2
GND2A
S2
INV2
LEVEL2
8
7
6
5
30
28
13
level
SWITCH
A2A
A2B
17
18
19
20
GND2B
OUT2Q
OUT2
GND2B
offset
LOS
DETECTOR
11
9
1×
26
RSSI2
LOSTH2
VEE2A
16
VEE2B
MGT028
Fig.1 Block diagram (TZA3019AHT and TZA3019AV).
2000 Apr 10
3
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level
detectors and 2
×
2 switch
TZA3019
handbook, full pagewidth
VEE1A
LOSTH1
32
10
25
VEE1B
LOS
DETECTOR
offset
12
29
31
1
2
3
4
A1A
A1B
5 kΩ
27
LOS1
TZA3019BHT
TZA3019BV
level
LEVEL1
INV1
S1
GND1A
IN1
IN1Q
GND1A
24
SWITCH
23
22
21
GND1B
OUT1
OUT1Q
GND1B
TEST
15
DFT
BAND GAP
REFERENCE
14
Vref
GND2A
IN2Q
IN2
GND2A
S2
INV2
LEVEL2
8
7
6
5
30
28
13
level
SWITCH
A2A
A2B
17
18
19
20
GND2B
OUT2Q
OUT2
GND2B
offset
LOS
DETECTOR
11
9
1×
26
RSSI2
LOSTH2
VEE2A
16
VEE2B
MGT027
Fig.2 Block diagram (TZA3019BHT and TZA3019AV).
2000 Apr 10
4
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level
detectors and 2
×
2 switch
TZA3019
handbook, full pagewidth
VEE1A
LOSTH1
32
10
25
VEE1B
LOS
DETECTOR
offset
12
29
31
1
2
3
4
A1A
A1B
5 kΩ
27
LOS1
TZA3019CHT
TZA3019CV
level
LEVEL1
INV1
S1
GND1A
IN1
IN1Q
GND1A
24
SWITCH
23
22
21
GND1B
OUT1
OUT1Q
GND1B
TEST
15
DFT
BAND GAP
REFERENCE
14
Vref
GND2A
IN2Q
IN2
GND2A
S2
INV2
LEVEL2
8
7
6
5
30
28
13
level
SWITCH
A2A
A2B
17
18
19
20
GND2B
OUT2Q
OUT2
GND2B
LOS
DETECTOR
offset
5 kΩ
26
LOS2
LOSTH2
VEE2A
11
9
16
VEE2B
MGS553
Fig.3 Block diagram (TZA3019CHT and TZA3019CV).
2000 Apr 10
5
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