32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
SMALL-OUTLINE
SDRAM MODULE
Features
• PC100 and PC133 compliant 144-pin, small-outline,
dual in-line memory module (SODIMM)
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 32MB (4Meg x 64), 64MB (8 Meg x 64), and 128MB
(16 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode: Standard and Low Power
• 32MB and 64MB: 64ms, 4,096-cycle refresh
(15.625µs refresh interval); 128MB: 64ms, 8,192-
cycle refresh (7.81µs refresh interval)
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
MT4LSDT464(L)H(I) – 32MB
MT4LSDT864(L)H(I) – 64MB
MT4LSDT1664(L)H(I) – 128MB
For the latest data sheet, please refer to the Micron
®
Web
site:
www.micron.com/products/modules
Figure 1: 144-Pin SODIMM (MO-190)
Standard 1.00in. (25.40 mm)
Options
• Self Refresh Current
Standard
Low-Power
• Operating Temperature Range
Commercial (0°C to + 65°C
)
Industrial (-40°C to +85°C)
• Package
144-pin SODIMM (standard)
144-pin SODIMM (lead-free)
• Memory Clock/CAS Latency
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
10ns (100 MHz)/CL = 2
NOTE:
Marking
None
L
1, 2
None
I
1, 2
G
Y
1
• Gold edge contacts
Table 1:
Timing Parameters
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
6ns2
–
5.4ns
–
SETUP HOLD
TIME TIME
1.5ns
1.5ns
2ns
0.8ns
0.8ns
1ns
-13E
-133
-10E
1. Contact Micron for product availability.
2. Low Power and Industrial Temperature options
not available concurrently; Industrial Tempera-
ture option available in -133 speed only.
Table 2:
Address Table
32MB
64MB
4K
4 (BA0, BA1)
128Mb (8 Meg x 16)
4K (A0–A11)
512 (A0–A8)
1 (S0#)
128MB
8K
4 (BA0, BA1)
256Mb (16 Meg x 16)
8K (A0–A12)
512 (A0–A8)
1 (S0#)
4K
4 (BA0, BA1)
64Mb (4 Meg x16)
4K (A0–A11)
256 (A0–A7)
1 (S0#)
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
Part Numbers
PART NUMBER
MT4LSDT464(L)HG-13E_
MT4LSDT464(L)HY-13E_
MT4LSDT464(L)H(I)G-133_
MT4LSDT464(L)H(I)Y-133_
MT4LSDT464(L)HG-10E_
MT4LSDT464(L)HY-10E_
MT4LSDT864(L)HG-13E_
MT4LSDT864(L)HY-13E_
MT4LSDT864(L)H(I)G-133_
MT4LSDT864(L)H(I)Y-133_
MT4LSDT864(L)HG-10E_
MT4LSDT864(L)HY-10E_
MT4LSDT1664(L)HG-13E_
MT4LSDT1664(L)HY-13E_
MT4LSDT1664(L)H(I)G-133_
MT4LSDT1664(L)H(I)Y-133_
MT4LSDT1664(L)HG-10E_
MT4LSDT1664(L)HY-10E_
NOTE:
MODULE DENSITY
32MB
32MB
32MB
32MB
32MB
32MB
64MB
64MB
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB
128MB
128MB
CONFIGURATION
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
SYSTEM
BUS SPEED
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
1. The designators for component and PCB revision are the last two characters of each part number. Consult factory for
current revision codes. Example: MT4LSDT1664HG-133B1
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
Table 3:
Pin Assignment
(144-Pin SODIMM Front)
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
DQ14
DQ15
V
SS
DNU
DNU
CK0
V
DD
RAS#
WE#
S0#
DNU
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
NC
V
SS
DNU
DNU
V
DD
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
DD
A6
A8
Vss
109
A9
111
A10
113
V
DD
115 DQMB2
117 DQMB3
119
Vss
121 DQ24
123 DQ25
125 DQ26
127 DQ27
129
V
DD
131 DQ28
133 DQ29
135 DQ30
137 DQ31
139
V
SS
141
SDA
143
V
DD
Table 4:
Pin Assignment
(144-Pin SODIMM Back)
38
DQ40
40
DQ41
42
DQ42
44
DQ43
46
V
DD
48
DQ44
50
DQ45
52
DQ46
54
DQ47
56
V
SS
58
DNU
60
DNU
62
CKE0
64
V
DD
66
CAS#
68
DNU
70 NC/A12
1
72
NC
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
DNU
V
SS
DNU
DNU
V
DD
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
110
BA1
112
A11
114
V
DD
116 DQMB6
118 DQMB7
120
V
SS
122 DQ56
124 DQ57
126 DQ58
128 DQ59
130
V
DD
132 DQ60
134 DQ61
136 DQ62
138 DQ63
140
V
SS
142
SCL
144
V
DD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQMB4
DQMB5
V
DD
A3
A4
A5
V
SS
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
Vss
DQMB0
DQMB1
V
DD
A0
A1
A2
V
SS
1. Pin 70 is No Connect for 32MB and 64MB modules, or A12 for 128MB modules.
Figure 2: 144-Pin SODIMM Pin Locations
Front View
Back View
U1
U2
U5
U4
U3
PIN 1
(all odd pins)
PIN 143
PIN 144
(all even pins)
PIN 2
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
Table 5:
Pin Descriptions
SYMBOL
RAS#, CAS#, WE#
CK0
TYPE
Input
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 more information
PIN NUMBERS
65, 66, 67
61
62
CKE0
69
S0#
23, 24, 25, 26, 115, 116, 117,
118
DQMB0–DQMB7
106, 110
BA0, BA1
29, 30, 31,32, 33, 34,
70
(128MB),
103, 104, 105,
109, 111, 112
A0–A11
(32MB, 64MB)
A0–A12
(128MB)
142
141
SCL
SDA
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle), ACTIVE POWER-DOWN (row ACTIVE in any device bank)
or CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Input Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Input Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Input Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-
detect portion of the module.
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
Table 5:
Pin Descriptions
SYMBOL
DQ0–DQ63
TYPE
Input/ Data I/O: Data bus.
Output
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 more information
PIN NUMBERS
3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15,
16, 17, 18, 19, 20, 37, 38, 39,
40, 41, 43, 44, 47, 48, 49, 50,
51, 52, 53, 54, 83, 84, 85, 86,
87, 88, 89, 90, 93, 94, 95, 96,
97, 98, 99, 100, 121, 122, 123,
124, 125, 126, 127, 128, 131,
132, 133, 134, 135, 136, 137,
138
11, 12, 27, 28, 45, 46, 63, 64,
81, 82, 101, 102, 113, 114, 129,
130, 143, 144
1, 2, 21, 22, 35, 36, 55, 56, 75,
76, 91, 92, 107, 108, 119, 120,
139, 140
70 (32MB, 64MB), 72, 73
57, 58, 59, 60, 68, 71, 74, 77,
78, 79, 80
V
DD
Supply Power Supply: +3.3V ±0.3V.
V
SS
Supply Ground.
NC
DNU
–
–
Not Connected: These pins should be left unconnected.
Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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