CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
SYMBOL
VIH
V
CC
= +5.0V ± 10%, Includes all Temperature Ranges
MIN
2.0
2.2
MAX
-
-
0.8
-
-
0.4
+1
+10
10
UNITS
V
V
V
V
V
V
µA
µA
µA
TEST CONDITIONS
CX82C54, IX82C54
MD82C54
-
IOH = -2.5mA
IOH = -100µA
IOL = +2.5mA
VIN = GND or V
CC
DIP Pins 9,11,14-16,18-23
VOUT = GND or V
CC
DIP Pins 1-8
V
CC
= 5.5V, VIN = GND or V
CC
,
Outputs Open, Counters
Programmed
V
CC
= 5.5V,
CLK0 = CLK1 = CLK2 = 8MHz,
VIN = GND or V
CC
,
Outputs Open
PARAMETER
Logical One Input Voltage
VIL
VOH
Logical Zero Input Voltage
Output HIGH Voltage
-
3.0
V
CC
-0.4
VOL
II
IO
ICCSB
Output LOW Voltage
Input Leakage Current
Output Leakage Current
Standby Power Supply Current
-
-1
-10
-
ICCOP
Operating Power Supply Current
-
10
mA
Capacitance
SYMBOL
CIN
COUT
CI/O
NOTE:
T
A
= +25
o
C; All Measurements Referenced to Device GND, Note 1
PARAMETER
Input Capacitance
Output Capacitance
I/O Capacitance
TYP
20
20
20
UNITS
pF
pF
pF
TEST CONDITIONS
FREQ = 1MHz
FREQ = 1MHz
FREQ = 1MHz
1. Not tested, but characterized at initial design and at major process/design changes.
3
82C54
AC Electrical Specifications
V
CC
= +5.0V ± 10%, Includes all Temperature Ranges
82C54
SYMBOL
READ CYCLE
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
TAR
TSR
TRA
TRR
TRD
TAD
TDF
TRV
Address Stable Before RD
CS Stable Before RD
Address Hold Time After RD
RD Pulse Width
Data Delay from RD
Data Delay from Address
RD to Data Floating
Command Recovery Time
30
0
0
150
-
-
5
200
-
-
-
-
120
210
85
-
25
0
0
95
-
-
5
165
-
-
-
-
85
185
65
-
25
0
0
95
-
-
5
165
-
-
-
-
85
185
65
-
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
2, Note 1
PARAMETER
MIN
MAX
82C54-10
MIN
MAX
82C54-12
MIN
MAX
UNITS
TEST
CONDITIONS
WRITE CYCLE
(9)
(10)
(11)
(12)
(13)
(14)
(15)
TAW
TSW
TWA
TWW
TDW
TWD
TRV
Address Stable Before WR
CS Stable Before WR
Address Hold Time After WR
WR Pulse Width
Data Setup Time Before WR
Data Hold Time After WR
Command Recovery Time
0
0
0
95
140
25
200
-
-
-
-
-
-
-
0
0
0
95
95
0
165
-
-
-
-
-
-
-
0
0
0
95
95
0
165
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
CLOCK AND GATE
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
NOTE:
1. Not tested, but characterized at initial design and at major process/design changes.
TCLK
TPWH
TPWL
TR
TF
TGW
TGL
TGS
TGH
TOD
TODG
TWO
TWC
TWG
TCL
Clock Period
High Pulse Width
Low Pulse Width
Clock Rise Time
Clock Fall Time
Gate Width High
Gate Width Low
Gate Setup Time to CLK
Gate Hold Time After CLK
Output Delay from CLK
Output Delay from Gate
OUT Delay from Mode Write
CLK Delay for Loading
Gate Delay for Sampling
CLK Setup for Count Latch
125
60
60
-
-
50
50
50
50
-
-
-
0
-5
-40
DC
-
-
25
25
-
-
-
-
150
120
260
55
40
40
100
30
40
-
-
50
50
40
50
-
-
-
0
-5
-40
DC
-
-
25
25
-
-
-
-
100
100
240
55
40
40
80
30
30
-
-
50
50
40
50
-
-
-
0
-5
-40
DC
-
-
25
25
-
-
-
-
100
100
240
55
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
4
82C54
Functional Diagram
DATA/
BUS
BUFFER
CLK 0
COUNTER
0
GATE 0
OUT 0
CONTROL
WORD
REGISTER
RD
WR
A
0
A
1
CS
READ/
WRITE
LOGIC
INTERNAL BUS
COUNTER
1
CLK 1
GATE 1
OUT 1
CONTROL
LOGIC
CE
STATUS
LATCH
CR
M
STATUS
REGISTER
CR
L
INTERNAL BUS
D
7
- D
0
8
CLK 2
CONTROL
WORD
REGISTER
COUNTER
2
GATE 2
OUT 2
GATE n
CLK n
OUT n
OL
M
OL
L
COUNTER INTERNAL BLOCK DIAGRAM
Pin Description
SYMBOL
D7 - D0
CLK 0
OUT 0
GATE 0
GND
OUT 1
GATE 1
CLK 1
GATE 2
OUT 2
CLK 2
A0, A1
DIP PIN
NUMBER
1-8
9
10
11
12
13
14
15
16
17
18
19 - 20
O
I
I
I
O
I
I
TYPE
I/O
I
O
I
DEFINITION
DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLOCK 0: Clock input of Counter 0.
OUT 0: Output of Counter 0.
GATE 0: Gate input of Counter 0.
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 1: Clock input of Counter 1.
GATE 2: Gate input of Counter 2.
OUT 2: Output of Counter 2.
CLOCK 2: Clock input of Counter 2.
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1
0
0
1
1
CS
RD
WR
V
CC
21
22
23
24
I
I
I
-
A0
0
1
0
1
SELECTS
Counter 0
Counter 1
Counter 2
Control Word Register
CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR
are ignored otherwise.
READ: This input is low during CPU read operations.
WRITE: This input is low during CPU write operations.
V
CC
: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for
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