NCP1589L
Low Voltage Synchronous
Buck Controller with Light
Load Efficiency and
Transient Enhancement
The NCP1589L is a low cost PWM controller designed to operate
from a 5 V or 12 V supply. This device is capable of producing an
output voltage as low as 0.8 V and converting voltage from as low as
2.5 V. It is easy to operate and provides an optimal level of integration
to reduce size and cost of the power supply. It operates in Ramp Pulse
Modulation mode for superior load step and release response. In
addition to fast transient response, it also includes a 1.5 A gate driver
design and light load efficiency features such as adaptive non−overlap
circuitry and diode emulation. It normally operates at a range of
200−500 kHz in continuous current conduction mode, which reduces
with current at light load for further power saving. Protection features
include programmable overcurrent protection, output overvoltage and
undervoltage protection and input undervoltage lockout (UVLO).
Features
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MARKING
DIAGRAM
1589L
ALYWG
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
DFN10
CASE 485C
1589L
A
L
Y
W
G
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
CC
Range from 4.5 V to 13.2 V
Adjustable Operating frequency
Boost Pin Operates to 35 V
Ramp Pulse Modulation Control
Precision 0.8 V Internal Reference
Adjustable Output Voltage
Internal 1.5 A Gate Drivers
80% Max Duty Cycle
Input Under Voltage Lockout
Programmable Current Limit
Adaptive Diode Mode Emulation in Light Load
This is a Pb−Free Device
Graphics Cards
Desktop Computers
Servers / Networking
DSP & FPGA Power Supply
DC−DC Regulator Modules
PIN CONNECTIONS
BOOT
LX
UG
LG
GND
1
2
3
4
5
Flag
10
9
8
7
6
PGOOD
VORPM
FB
COMP/DIS
V
CC
(Top View)
Applications
ORDERING INFORMATION
Device
NCP1589LMNTWG
Package
DFN10
(Pb−Free)
Shipping
†
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2013
August, 2013
−
Rev. 2
1
Publication Order Number:
NCP1589L/D
NCP1589L
V
CC
= 4.5 V
−
13.2 V
V
BST
= 4.5 V
−
15 V
V
IN
= 2.5 V
−
19 V
VCC
PGOOD
COMP/DIS
C1
R2
C2
FB
FLAG
C3
R4
R1
R3
R9
R10
GND
LX
LG
GND VORPM
ROCSET
VOUT
BOOT
UG
Figure 1. Typical Application Diagram
PGOOD
10
VORPM 9
PGOOD
MONITOR
OV and UV
0.8 V
(V
ref
)
±10%
of V
ref
±25%
of V
ref
POR
UVLO
6
VCC
FAULT
FB
8
−
+
0.8 V
(V
ref
)
LATCH
+
−
FAULT
VOCP
1
3
2
BOOT
UG
LX
−
+
R
S
PWM
OUT
Q
+
RPMSET
RAMP
COMP VPRM
COMP/DIS
7
LX
VORPM
−
+
−
2V
VCC
4
5
AZCD logic
LG
GND
FAULT
LX
Figure 2. Detailed Block Diagram
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2
NCP1589L
PIN FUNCTION DESCRIPTION
Pin No.
1
Symbol
BOOT
Description
Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired
input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (C
BOOT
) between this pin and
the LX pin. Typical values for C
BOOT
range from 0.1
mF
to 1
mF.
Ensure that C
BOOT
is placed near the IC.
Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top
MOSFET. Also used for low side MOSFET R
DS(on)
current detection and diode emulation.
Top gate MOSFET driver pin. Connect this pin to the gate of the top N−channel MOSFET.
Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−channel MOSFET. Also used to
set the overcurrent limit.
IC ground reference. All control circuits are referenced to this pin. Connect to FLAG.
Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1
mF
capacitor
to GND. Ensure that this decoupling capacitor is placed near the IC. Also low−side MOSFET drive voltage.
Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM com-
parator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. Pull this
pin low for disable.
This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to com-
pensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly
to V
out
.
Output voltage information for RPM threshold
Power Good output. Pulled Low if VFB is outside
±10%
of 0.8 V V
ref
.
2
3
4
5
6
7
LX
UG
LG
GND
VCC
COMP/DIS
8
FB
9
10
VORPM
PGOOD
ABSOLUTE MAXIMUM RATINGS
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage Input
Symbol
VCC
BOOT
V
MAX
15 V
35 V wrt/GND
40 V < 100 ns
15 V wrt/LX
35 V
40 V for < 100 ns
30 V wrt/GND
15 V wrt/LX
40 V for < 100 ns
15 V
6.0 V
5.5 V
7V
V
MIN
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−5
V
−10
V for < 200 ns
−0.3
V wrt/LX
−5
V for < 200 ns
−0.3
V
−5
V for < 200 ns
−0.3
V
−0.3
V
−0.3
V
Switching Node (Bootstrap Supply Return)
High−Side Driver Output (Top Gate)
LX
UG
Low−Side Driver Output (Bottom Gate)
Feedback, VORPM
COMP/DIS
PGOOD
LG
FB, VORPM
COMP/DIS
PGOOD
MAXIMUM RATINGS
Rating
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
Symbol
R
qJA
R
qJC
T
J
T
A
T
stg
MSL
Value
165
45
0 to 150
0 to 95
−55
to +150
1
Unit
°C/W
°C/W
°C
°C
°C
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
NCP1589L
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< 95°C; 4.5 V < [BOOT−LX] < 13.2 V, 4.5 V < BOOT < 30 V, 0 V < LX < 21 V,
C
TG
= C
BG
= 1.0 nF, for min/max values unless otherwise noted.)
Characteristic
V
CC
Input Voltage Range
BOOT Voltage Range
dV/dt on V
CC
VREF AND ERROR AMPLIFIER
Reference Voltage
Output Voltage Accuracy
SUPPLY CURRENT
V
CC
Quiescent Supply Current
BOOT Quiescent Current
UNDERVOLTAGE LOCKOUT
V
CC
UVLO Threshold
V
CC
UVLO Threshold
V
CC
UVLO Hysteresis
SWITCHING REGULATOR
Ramp Slope
Ramp−Amplitude Voltage
Minimum Duty Cycle
Maximum Duty Cycle
LG Minimum on Time
ERROR AMPLIFIER
Open Loop DC Gain (Note 1)
Output Source Current
Output Sink Current
Unity Gain Bandwidth (Note 1)
Disable Threshold
Output Source Current During Disable
GATE DRIVERS
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
UG Falling to LG Rising Delay Tdead1
(Note 1)
LG Falling to UG Rising Delay Tdead2
(Note 1)
UG Internal Resistor to LX
LX Internal Resistor to GND
SOFT−START
Soft−Start Time
Enable to Soft−Start Delay (Note 1)
V
CC
> 4.5 V, COMP
w
Disable Threshold
V
CC
> 4.5 V, COMP Rises and Crosses
Disable Threshold
2.0
2.6
500
ms
ms
BOOT
−
LX = 5 V
BOOT
−
LX = 5 V
V
CC
= 5 V
V
CC
= 5 V
V
CC
= 12 V, UG−LX < 1.0 V, LG > 1.0 V
Only Valid for CCM Operating Mode
V
CC
= 12 V, LG < 1.0 V, UG > 1.0 V
Only Valid for CCM Operating Mode
Unbiased, BOOT
−
LX = 0
1.5
1.2
20
20
45
45
30
30
1.5
1.8
A
W
A
W
ns
ns
kW
kW
V
fb
< 0.8 V
V
fb
> 0.8 V
80
2.0
2.0
15
0.7
0.8
10
0.9
40
120
dB
mA
MHz
V
mA
70
200
0.5
1.50
0
83
92
350
V/ms
V
%
%
ns
V
CC
Rising
V
CC
Falling
V
CC
Rising or V
CC
Falling
4.4
4.0
400
V
V
mV
No Switching, V
CC
= 13.2 V
No Switching
0.1
2.5
3.8
100
mA
mA
Vref
Reference and Error Amplifier Excluding
External Resistive Divider Tolerance
−1.0
0.8
1.0
V
%
13.2 V wrt LX
Conditions
Min
4.5
4.5
−10
Typ
Max
13.2
30
10
Unit
V
V
V/ms
1. Guaranteed by design but not tested in production.
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4
NCP1589L
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< 95°C; 4.5 V < [BOOT−LX] < 13.2 V, 4.5 V < BOOT < 30 V, 0 V < LX < 21 V,
C
TG
= C
BG
= 1.0 nF, for min/max values unless otherwise noted.)
Characteristic
POWER GOOD INCLUDING OVP AND UVP THRESHOLD
Output Voltage
Overvoltage until PGOOD goes low
Undervoltage until PGOOD goes low
PGOOD High Upper Limit Hysteresis
PGOOD High Lower Limit Hysteresis
OVP Threshold to Part Disable
UVP Threshold to Part Disable
Power Good Delay (Note 1)
ZERO CURRENT DETECTION
(LX Pin)
Zero Current Detection Blank Timer after
TG < 1.0 V
Capture Time for LX Voltage (Note 1)
LX > 50 mV, LG on time
Time to Capture LX Voltage Once LG is <
1.0 V
200
250
350
40
ns
ns
950
570
698
Logic Low, Sinking 4 mA
880
720
16
16
1000
600
1030
630
1.0
0.4
902
V
mV
mV
mV
mV
mV
mV
ms
Conditions
Min
Typ
Max
Unit
ZERO CURRENT V
th
ADJUSTMENT DETECTION
(LX Pin)
Negative LX Detection Voltage
Positive LX Detection Voltage
Time for V
th
Adjustment and Settling Time
Zero Current Detection Blank Timer after
LG < 1.0 V (Note 1)
Initial Negative Current Detection
Threshold Voltage Setpoint (Note 1)
V
th
Adjustable Range (Note 1)
OVERCURRENT PROTECTION
OC Current Source
OCP Programming Time
Sourced from LG pin, before SS
V
CC
> 4.5 V, R
oscset
= 60 kW
9.5
1.0
10
10.5
5.0
mA
ms
Vbdls
Vbdhs
300 kHz
Blanking Time After LG is < 1.0 V
LX−GND, Includes
$2
mV Offset Range
−5.0
−16
−3.0
0
200
0.2
3.0
300
0.5
400
1.0
3.7
40
−1.0
15
mV
V
ms
ns
mV
mV
1. Guaranteed by design but not tested in production.
Phase
Ugate to Phase
1V
Lgate
Tdead1
Tdead2
Figure 3. Dead Time Definition
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5
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