Data Sheet
March 2005
LCK4953/L-LCK4953
Low-Voltage PLL Clock Driver
Features
■
■
■
■
■
■
Fully integrated PLL.
Output frequency up to 130 MHz in PLL mode.
Nine outputs with high-impedance disable.
32-lead TQFP.
50 ps cycle-to-cycle jitter.
Pin compatible with the
Motorola
®
MPC953 clock
driver.
The LCK4953 is fully 3.3 V compatible and requires
no external loop filter components. All control inputs
accept LVCMOS or LVTTL compatible levels while
the outputs provide LVCMOS levels with the ability to
drive terminated 50
Ω
transmission lines. For series-
terminated 50
Ω
lines, each of the LCK4953 outputs
can drive two traces giving the device an effective
fan-out of 1:18. For the optimum combination of
board density and performance, the device is
packaged in a 7 mm
×
7 mm 32-lead TQFP package.
The L-LCK4953 is a lead-free device.
Table 1. Function Table
Description
The LCK4953 is a PLL-based clock driver device
intended for high-performance clock tree designs.
The LCK4953 is 3.3 V compatible with output
frequencies of up to 130 MHz and output skews of
75 ps. The LCK4953 can meet the most demanding
timing requirements and employs on-chip voltage
regulators to minimize cycle-to-cycle jitter and phase
jitter.
The LCK4953 is ideal for use as a zero delay, low
skew, fan-out buffer due to its differential LVPECL
reference input along with an external feedback
input. The MROEB pin of the LCK4953, when driven
high, will reset the internal counters and 3-state the
output buffers. The LCK4953 has been optimized for
zero delay performance.
BYPASSB
1
0
MROEB
1
0
VCOSEL
1
0
PLLEN
1
0
Function
PLL Enabled
PLL Bypass
Function
Outputs Disabled
Outputs Enabled
Function
÷
8
÷
4
Function
Select VCO
Select PELCLK
LCK4953/L-LCK4953
Low-Voltage PLL Clock Driver
Data Sheet
March 2005
Description
(continued)
BYPASSB
VCOSEL
PLLEN
QFB
V
DD
V
SS
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
A
FBCLK
NC1
NC2
NC3
NC4
V
SS
A
PECLCKP
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
9
V
SS
Q0
Q1
V
DD
Q2
V
SS
Q3
V
DD
Q4
V
SS
LCK4953/L-LCK4953
20
19
18
17
V
DD
V
SS
PECLCKN
V
DD
Q7
Q6
MROEB
Q5
5-8653(F)
Figure 1. 32-Lead Pinout (Top View)
Absolute Maximum Ratings
Stresses which exceed the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods of time can adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Input Current
Storage Temperature Range
Symbol
V
DD
V
IN
I
IN
T
stg
Min
–0.3
–0.3
—
–40
Max
4.2
V
DD
+ 0.3
±20
125
Unit
V
V
mA
°C
Notes:
Lead free: No intentional addition of lead, and less than 1000 ppm.
Agere Systems lead-free devices are fully compliant with the Restriction of Hazardous Substances (RoHS) directive that restricts the content of
six hazardous substances in electronic equipment in the European Union. Beginning July 1, 2006, electronic equipment sold in the European
Union must be manufactured in accordance with the standards set by the RoHS directive.
External leads can be bonded and soldered safely at temperatures of up to 300 °C on non-lead-free parts and up to 350 °C on lead-free parts.
2
Agere Systems Inc.
Data Sheet
March 2005
LCK4953/L-LCK4953
Low-Voltage PLL Clock Driver
Absolute Maximum Ratings
(continued)
Table 3. dc Characteristics
(T
A
= 0
°C
to 70
°C,
V
DD
= 3.3 V
±
5%)
Parameter
Input High-voltage LVCMOS
Inputs
Input Low-voltage LVCMOS
Inputs
Peak-to-peak Input Voltage
PECL_CLK
Common-mode Range
PECL_CLK
Output High Voltage
Output Low Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum Quiescent Supply
Current Non-PLL
Maximum PLL Supply Current
Symbol
V
IH
V
IL
Vp-p
V
CMR
V
OH
V
OL
I
IN
C
IN
Cpd
I
DDQ
I
DDPLL
Min
2.0
—
300
V
DD
– 1.5
2.4
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
12
—
—
Max
3.6
0.8
1000
V
DD
– 0.6
—
0.6
±120
4
—
1
45
Unit
V
V
mV
mV
V
V
µA
pF
pF
mA
mA
Condition
—
—
—
—
*
I
OH
= –30 mA
†
I
OL
= 30 mA
†
—
—
Per output
All V
DD
pins except
V
DD
A
‡
V
DD
A pin only
* V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the high input is within
the V
CMR
range and the input swing lies within the Vp-p specification.
† The LCK4953 outputs can drive series- or parallel-terminated 50
Ω
(or 50
Ω
to V
CC
/2) transmission lines on the incident edge.
‡ Total power = (I
DDPLL
+ I
DDQ
+ fCV) * V; where f = fref, V = V
DDD
, C = total load capacitance on all outputs.
Table 4. PLL Input Reference Characteristics
(T
A
= 0
°C
to 70
°C)
Parameter
Reference Input Frequency
Reference Input Duty Cycle
Symbol
fref
trefdc
Min
25
25
Max
130
75
Unit
MHz
%
Condition
—
—
Table 5. ac Characteristics
(T
A
= 0
°C
to 70
°C,
V
DD
= 3.3 V
±
5%)
Parameter
Output Rise/Fall Time
Output Duty Cycle
Output-to-output Skews
PLL V
CO
Lock Range
Frequency Output:
Frequency PLL
Bypass Mode
Input to Ext_FB Delay (with PLL locked)
Input to Q Delay
Part to Part Delay
Output Disable Time
Output Enable Time
Cycle-to-cycle Jitter (peak-to-peak)
Symbol
tr, tf
tpw
tsk(O)
fV
CO
fout
Min
0.10
47
—
200
25
50
—
–75
3
—
—
—
Typ
—
50
—
—
—
—
—
—
—
—
—
—
Max
1.0
53
75
520
65
130
250
125
7
1.5
7
6
50
Unit
ns
%
ps
MHz
MHz
MHz
MHz
ps
ns
ns
ns
ps
Condition
0.8 V to 2.0 V
—
—
—
VCOSEL = 1
VCOSEL = 0
—
tref = 75 MHz
PLL bypassed
—
—
fout > 75 MHz
tpd (lock)
tpd(bypass)
tPLZHZ
tPZL
tjitter
Agere Systems Inc.
3
LCK4953/L-LCK4953
Low-Voltage PLL Clock Driver
Data Sheet
March 2005
Electrical Characteristics
PECLCKP
PECLCKN
P
N
D0
A
/4
Z
A
/2
Z
D1
SD
Z
D0
Z
D1
SD
Z
Q[0:6]
Z
PAD
Q7
Q[0:6]
QFB
D0
D1
SD
Z
Z
PAD
QFB
DIVBY4
DIVBY2
D0
FBCLK
PLL CORE
A
/4
Z
A
/2
Z
D1
SD
Q7
Z
PAD
DIVBY4
DIVBY2
PLLEN
VCOSEL
BYPASSB
MROEN
5-8654.a (F)
Figure 2. Logic Diagram
Power Supply Filtering
The LCK4953 is a mixed-signal product that is susceptible to random noise, especially when this noise is on the
power supply pins. To isolate the output buffer switching from the internal phase-locked loop, the LCK4953
provides separate power supplies for the phase-locked loop (V
DD
A) and for the output buffers (V
DD
). In a digital
system environment, besides this isolation technique, it is highly recommended that both V
DDA
and V
DD
power
supplies be filtered to reduce the random noise as much as possible.
Figure 3 illustrates a typical power supply filter scheme. A filter for the LCK4953 should be designed to target noise
in the 100 kHz to 10 MHz range, due to the LCK4953’s susceptibility to noise with spectral content in this range.
The RC filter in Figure 3 will provide a broadband filter with approximately –40 dB attenuation for noise with
spectral content above 20 kHz. More elaborate power supply schemes may be used to achieve increased power
supply noise filtering.
3.3 V
R
S =
5
Ω—10 Ω
V
DDA
0.01
µF
LCK4953
V
DD
0.01
µF
22
µF
5-9575(F)
Figure 3. Power Supply Filter
4
Agere Systems Inc.
Data Sheet
March 2005
LCK4953/L-LCK4953
Low-Voltage PLL Clock Driver
Electrical Characteristics
(continued)
Driving Transmission Lines
The LCK4953 clock driver was designed to drive high-speed clock terminals in a terminated transmission line
environment. Point-to-point distribution of signals is a common method in most high-performance clock networks.
Either series-terminated or parallel-terminated transmission lines can be used in a point-to-point scheme. The
parallel technique terminates the signal at the end of a line with a 50
Ω
resistance to V
DD
/2. This draws a fairly high
level of dc current. Due to this aspect, only a single terminated line can be driven by each output of the LCK4953
clock driver. However, for the series-terminated case, there is no dc current draw. Therefore, the outputs are
capable of driving multiple series-terminated lines.
Figure 4 illustrates an output driving a single series-terminated line.
OUTPUT
BUFFER
OUTPUT
CLOCK
14
Ω
R
S
= 36
Ω
Z
O
= 50
Ω
5-9576(F)
Figure 4. Single Transmission Line
In Figure 4, because the output buffer has an impedance of 14
Ω,
the series resistance (R
s
) is set at 36
Ω.
This
ensures that the total impedance is matched with the 50
Ω
transmission line.
Figure 5 illustrates an output driving two series-terminated lines.
R
S
= 22
Ω
OUTPUT
BUFFER
OUTPUT
CLOCK
14
Ω
R
S
= 22
Ω
Z
O
= 50
Ω
Z
O
= 50
Ω
5-9577(F)
Figure 5. Dual Transmission Lines
In Figure 5, the two series resistors (R
s)
are set at 22
Ω
because the 14
Ω
output buffer can be viewed as two 28
Ω
resistors in parallel. Accordingly, for each transmission line, the impedance is well matched.
Agere Systems Inc.
5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
