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USE GAL DEVICES FOR NEW DESIGNS
FINAL
COM’L: H-15/25
PALCE610 Family
DISTINCTIVE CHARACTERISTICS
s
Lattice/Vantis Programmable Array Logic (PAL)
architecture
s
Electrically-erasable CMOS technology
providing half power (90 mA I
CC
) at high speed
— -15 = 15-ns t
PD
— -25 = 25-ns t
PD
s
Sixteen macrocells with configurable I/O
architecture
s
Registered or combinatorial operation
s
Registers programmable as D, T, J-K, or S-R
Lattice Semiconductor
EE CMOS High Performance Programmable Array Logic
s
Asynchronous clocking via product term or
bank register clocking from external pins
s
Register preload for testability
s
Power-up reset for initialization
s
Space-saving 24-pin SKINNYDIP and 28-pin
PLCC packages
s
Fully tested for 100% programming yield and
high reliability
s
Extensive third-party software and programmer
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE610 is a general purpose PAL device and is
functionally and fuse map equivalent to the EP610. It
can accommodate logic functions with up to 20 inputs
and 16 outputs. There are 16 I/O macrocells that can be
individually configured to the user’s specifications. The
macrocells can be configured as either registered or
combinatorial. The registers can be configured as D, T,
J-K, or S-R flip-flops.
The PALCE610 uses the familiar sum-of-products logic
with programmable-AND and fixed-OR structure. Eight
product terms are brought to each macrocell to provide
logic implementations.
The PALCE610 is manufactured using advanced
CMOS EE technology providing low power consump-
tion. Moreover, it is a high-speed device having a worst-
case t
PD
of 15 ns. Space-saving 24-pin SKINNYDIP and
28-pin PLCC packages are offered.
This device can be quickly erased and reprogrammed
providing for easy prototyping. Once a device is pro-
grammed the security bit can be used to provide protec-
tion from copying a proprietary design.
BLOCK DIAGRAM
I
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
CLK1
4
2 8
2 8
2 8
2 8
2 8
Programmable AND Array
40 x 160
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
CLK2
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
12950G-1
Amendment
/0
2-374
Publication#
12950
Rev.
G
Issue Date:
February 1996
CONNECTION DIAGRAMS
Top View
SKINNYDIP
CLK1
I
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I
I
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I
CLK2
12950G-2
PLCC/LCC
CLK1
V
CC
I/O
9
V
CC
I/O
1
4
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
NC
5
6
7
8
9
10
11
3
2
1 28 27 26
25
24
23
22
21
20
19
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
12 13 14 15 16 17 18
I/O
16
I
CLK2
GND
GND
I/O
8
12950G-3
Note:
Pin 1 is marked for orientation
PIN DESIGNATIONS
CLK
GND
I
I/O
NC
V
CC
=
=
=
=
=
=
Clock
Ground
Input
Input/Output
No Connect
Supply Voltage
PALCE610 Family
I
I
2-375
ORDERING INFORMATION
Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
CE
610 H -15 P C
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
DEVICE NUMBER
610 = 600 Gates
POWER
H = Half Power (90 mA I
CC
)
SPEED
-15 = 15 ns t
PD
-
25 = 25 ns t
PD
OPERATING CONDITIONS
C = Commercial (0
°
C to +75
°
C)
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
Valid Combinations
PALCE610H-15
PC, JC
PALCE610H-25
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
your local sales office to confirm availability of
specific valid combinations, and to check on
newly released combinations.
2-376
PALCE610H-15/25 (Com’l)
FUNCTIONAL DESCRIPTION
The PALCE610 is a general purpose programmable
logic device. It has 16 independently-configurable ma-
crocells. Each macrocell can be configured as either
combinatorial or registered. The registers can be D, T,
J-K, or S-R type flip-flops. The device has 4 dedicated
input pins and 2 clock pins. Each clock pin controls 8 of
the 16 macrocells.
The programming matrix implements a programmable
AND logic array which drives a fixed OR logic array.
Buffers for device inputs have complementary outputs
to provide user-programmable input polarity. Unused in-
put pins should be tied to V
CC
or ground.
The array uses our electrically erasable technology.
An unprogrammed bit is disconnected and a pro-
grammed bit is connected. Product terms with all bits
unprogrammed assume the logical-HIGH state and
product terms with both the TRUE and Complement bits
programmed assume the logical-LOW state.
The programmable functions in the PALCE610 are
automatically configured from the user’s design specifi-
cations, which can be in a number of formats. The de-
sign specification is processed by development
software to verify the design and create a programming
file. This file, once downloaded to the programmer, con-
figures the design according to the user’s desired
function.
asynchronous configuration, the clock input is con-
trolled by the product term. The output is always
enabled.
In The D and T configurations, feedback can be either
from
Q
or the output pin. This allows D and T configura-
tions to be either outputs or I/O. In the J-K and S-R con-
figurations, feedback is only from
Q;
therefore, J-K and
S-R configurations are strictly outputs.
D Flip-Flop
All 8 product terms are available to the OR gate. The D
input polarity is controlled by an exclusive-OR gate. For
the D flip-flop, the output level is the D-input level at the
rising edge of the clock.
D
0
0
1
1
Q
n
0
1
0
1
Q
n+1
0
0
1
1
T Flip-Flop
All 8 product terms are available to the OR gate. The
T input polarity is controlled by an exclusive-OR gate.
For the T register, the output level toggles when the T
input is HIGH and remains the same when the T input is
LOW.
T
Q
n
0
1
0
1
Q
n+1
0
1
1
0
Macrocell Configurations
The PALCE610 macrocell can be configured as either
combinatorial or registered. Both the combinatorial and
registered configurations have output polarity control.
The register can be configured as a D, T, J-K, or
S-R type flip-flop. Figure 1 shows the possible
configurations.
Each macrocell can select as its clock either the corre-
sponding clock pin or the CLK/OE product term. If the
clock pin is selected, the output enable is controlled by
the CLK/OE product term. If the CLK/OE product term is
selected, the output is always enabled.
0
0
1
1
J-K Flip-Flop
The 8 product terms are divided between the J and K in-
puts. N product terms go to the J input and 8-N product
terms go to the K input, where N can range from 0 to 8.
Both the J and K inputs to the flip-flop have polarity con-
trol via exclusive-OR gates. The J-K flip-flop operation
is shown below.
J
0
0
0
0
1
1
1
1
K
0
0
1
1
0
0
1
1
Q
n
0
1
0
1
0
1
0
1
Q
n+1
0
1
0
0
1
1
1
0
Combinatorial I/O
All 8 product terms are available to the OR gate. The
output-enable function is performed by the CLK/OE
product term.
Registered Configurations
There are 4 flip-flop types available: D, T, J-K and S-R.
The registers can be configured as synchronous or
asynchronous. In the synchronous configuration, the
clock is controlled by the clock input pin. The output en-
able is controlled by the product term function. In the
PALCE610 Family
2-377
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