80387DX
Math Coprocessor
80387
Memory
Logic Diagram
F
EATURES
:
• 80-Bit numeric processor
• R
AD
-P
AK
® radiation hardened against natural space radia-
tion
• Total dose hardness:
- > 100 krad (Si)
- dependant upon space mission
• Single Event Effects:
- SEU Threshold is ~ 3.38 MeV/mg/cm
2
- SEL Threshold = 37.1 - 59.9 MeV/mg/cm
2
• Package: 68-pin R
AD
-P
A
® quad flat pack
• Eight 80-bit numeric registers, usable as individual addres-
sable general registers or as a register stack
• Data types include:
- 32-, 64-, 80-bit floating point
- 32-, 64-bit integers
- 18-digit BCD operands
• 5 V Only power
• Built-in exception handling
• Upward object code compatible with All 80X87DX micro-
processors
• Full-range transcendental operations for SINE, COSINE,
TANGENT, ARCTANGENT and LOGARITHM
D
ESCRIPTION
:
DDC's
80387DX high speed microcircuit features a greater
than 100 kilorad (Si) total dose tolerance. Using
DDC's
radiation hardened R
AD
-P
AK
® packaging technology, the
80387DX is a high-performance numerics processor that
extends the 80386DX architecture with floating point,
extended integer and BCD data types. The computing system
fully conforms to the ANSI/IEEE floating-point standard.
Using a numerics oriented architecture, the 80387DX adds
over seventy mnemonics to the 80386DX instruction set, mak-
ing the 80386DX/80387DX a complete solution for high-per-
formance numerics processing.
DDC's
patented R
AD
-P
AK
packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
05.07.02 REV 1
All data sheets are subject to change without notice
1
(631) 567-5600 - Fax: (631) 567-7358 - www.ddc-web.com
©2002 DDC
All rights reserved.
Math Coprocessor
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
1, 12, 19, 21, 35, 49, 53, 56
2, 13, 20, 32, 36, 39, 52, 68
S
YMBOL
V
SS
V
CC
Ground
Positive Power Supply
D
ESCRIPTION
80387DX
3-11, 18, 22-31, 33, 34, 37, D4-D12, D15, D16-25, D26, D27, Data Bus
38, 40, 41, 64-67
D28, D29, D30, D31, D0-D3
42
43
44
45
46
47 59
48
50
51
54
55
57
58
60
61
62
63
CKM
386CLK2
387CLK2
RESETIN
NC
Tie High
READY
CMD0
ADS
NPS2
NPS1
W/R
STEN
READYO
BUSY
ERROR
PEREQ
Clock Mode
386 CPU Clock 2
387 MCP Clock 2
System Reset
Not Connected
Tie High
Bus Ready Input
Command
Address Strobe
MCP Select #2
MCP Select #1
Write/Read
Status Enable
Ready Output
Busy Status
Error Status
Processor Extension Request
Memory
T
ABLE
2. A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Voltage, any pin, with respect to Ground
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering 10 seconds)
S
YMBOL
V
CC
P
D
T
S
T
A
M
IN
-0.5
--
-65
-55
--
M
AX
V
CC
+0.5
1.5
150
125
260
U
NIT
V
W
°
C
°
C
°
C
05.07.02 REV 1
All data sheets are subject to change without notice
2
©2002 DDC
All rights reserved.
Math Coprocessor
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
LI
I
LO
I
CC
CLK2 = 32 MHz
I
CC
CLK2 = 50 MHz
V
ARIATION
± 1.5 µ A
±1.5 µ A
±25 mA
±39 mA
80387DX
T
ABLE
4. R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temperature
S
YMBOL
V
CC
V
IL
V
IH
T
A
M
IN
4.75
-0.3
2.0
-55
M
AX
5.25
0.8
V
CC
+0.3
125
U
NIT
V
V
V
°C
Memory
T
ABLE
5. 80387DX DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 4.75V
TO
5.25V; T
A
= -55
TO
+125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Low Voltage
Input High Voltage
386 CLK2 Input Low Voltage
386 CLK2 Input High Voltage
Output Low Voltage
Output High Voltage
S
YMBOL
V
IL1
V
IH1
V
CL
V
CH
V
OL
V
OH
I
OL
= 4 mA, D0-D31, I
OL
= 2.5 mA
READYO , ERROR, BUSY, PEREQ
I
OH
= -1 mA, D0-D31, I
OH
= -0.6 mA
READYO, READYO, ERROR, BUSY,
PEREQ
0V < V
IN
< V
CC
0.45V < V
OUT
< V
CC
CLK2 = 32 MHz
CLK2 = 40 MHz
CLK2 = 50 MHz
2
F
C
= 1 MHz
F
C
= 1 MHz
F
C
= 1 MHz
--
--
--
--
--
--
--
T
EST
C
ONDITIONS
M
IN
--
--
2.0
--
3.7
--
2.4
M
AX
0.8
--
--
0.8
--
0.45
--
U
NIT
V
V
V
V
V
V
Input Leakage Current
Output Leakage Current
Power Supply Current
I
LI
I
LO
I
CC
±15
±15
250
310
390
10
12
20
µA
µA
mA
Input Capacitance
3
Output Capacitance
3
CLK2 Capacitance
3
C
IN
C
O
C
CLK
pF
pF
pF
1. This parameter is for all inputs, including 387CLK2 but excluding 386CLK2.
2. Icc is measured at steady state, maximum capacitive loading on the outputs, and worst-case DC level at the inputs;
386CLK2 at the same frequency as 387CLK2.
3. Guaranteed By Design
05.07.02 REV 1
All data sheets are subject to change without notice
3
©2002 DDC
All rights reserved.
Math Coprocessor
80387DX
T
ABLE
6. 80387DX C
OMBINATIONS OF
B
US
I
NTERFACE AND
E
XECUTION
S
PEEDS
(V
CC
= 4.75V
TO
5.25V; T
A
= -55
TO
+125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Bus INterface Unit
-16
-20
-25
Execution Unit
-16
-20
-25
S
YMBOL
T
EST
C
ONDITIONS
M
IN
16
20
25
16
20
25
M
AX
--
--
--
MHz
--
--
--
U
NIT
MHz
T
ABLE
7. 80387DX T
IMING
R
EQUIREMENTS OF
T
HE
E
XECUTION
U
NIT
(V
CC
= 4.75V
TO
5.25V; T
A
= -55
TO
+125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
387CLK2 Period
1
-16
-20
-25
387CLK2 High Time
-16
-20
-25
387CLK2 High Time
1
-16
-20
-25
387CLK2 Low Time
-16
-20
-25
387CLK2 Low Time
1
-16
-20
-25
387CLK2 Fall Time
1
-16
-20
-25
387CLK2 Rise Time
1
-16
-20
-25
1. Guaranteed By Design
S
YMBOL
t
1
At 2V
31
25
20
t
2a
At 2V
9
8
7
t
2b
At 3.7V
5
5
4
t
3a
At 2V
9
8
7
t
3b
At 0.8V
7
6
5
t
4
At 3.7V to 0.8V
--
--
--
t
5
At 0.8V to 3.7V
--
--
--
8
8
7
8
8
7
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
125
125
125
ns
T
EST
C
ONDITION
M
IN
M
AX
U
NIT
Memory
ns
05.07.02 REV 1
All data sheets are subject to change without notice
4
©2002 DDC
All rights reserved.
Math Coprocessor
(V
CC
= 4.75V
TO
5.25V; T
A
= -55
TO
+125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
386CLK2 Period
1
-16
-20
-25
386CLK2 High Time
-16
-20
-25
386CLK2 High Time1
-16
-20
-25
386CLK2 Low Time
-16
-20
-25
386CLK2 Low Time
1
-16
-20
-25
386CLK2 Fall Time
1
-16
-20
-25
386CLK2 Rise Time
1
-16
-20
-25
386 CLK2/387CLK2 Ratio
READYO Out Delay
-16
-20
-25
PEREQ, ERROR Out Delay
-16
-20
-25
BUSY Out Delay
-16
-20
-25
C
L
= 50 pF
At 2.0V
C
ONDITIONS
S
YMBOL
t
1
31
25
20
At 2.0V
t
2a
9
8
7
At 3.7V
t
2b
5
5
4
At 2V
t
3a
9
8
7
At 0.8V
t
3b
7
6
5
At 3.7V to 0.8V
t
4
--
--
--
At 0.8V to 3.7V
t
5
--
--
--
--
t
7
4
3
3
C
L
= 50 pF
t
7
5
5
4
C
L
= 50 pF
t
7
5
5
4
10/16
M
IN
80387DX
M
AX
125
125
125
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
8
8
7
ns
8
8
7
14/10
34
31
24
ns
34
34
33
ns
34
29
29
--
ns
U
NIT
ns
T
ABLE
8. 80387DX T
IMING
R
EQUIREMENTS OF
T
HE
B
US
I
NTERFACE
U
NIT
(O
UTPUT
T
RIP
L
EVEL
= 1.5V)
Memory
05.07.02 REV 1
All data sheets are subject to change without notice
5
©2002 DDC
All rights reserved.
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