HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Document Title
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Edit Pin Description table
2) Edit Data Protection texts
3) Add Read ID table
4) Add Marking Information
5) Add Application note
6) Change AC characteristics
tCLS tCLH
0.1
Before
After
10
0
5
10
tCS
15
0
tCH
5
10
tWP tALS
15
25
10
0
tDS
10
20
tDH
5
10
May. 23. 2005
Preliminary
History
Draft Date
Dec. 2004
Remark
Preliminary
tWC tWH
Before
After
30
50
10
15
tRP
15
25
tRC
30
50
tREA tREH tCEA
18
35
10
20
23
45
1) Add ULGA Package.
- Figures & texts are added.
2) Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
LI,
I
LO
)
Before
After
VIN=VOUT=0 to 3.6V
VIN=VOUT=0 to Vcc (max)
0.2
3) Change AC Conditions table
4) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
5) Add tRBSY (Table12)
- tRBSY (Dummy Busy Time for Cache Read)
- tRBSY is 5us (typ.)
- Figure 19,20 are edited.
6) Edit System Interface Using CE don’t care Figures.
Aug. 09. 2005
Preliminary
Rev 0.5 / Feb. 2006
1
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Revision History
Revision
No.
7) Change AC characteristics
tWH
0.2
Before
After
20
(4)
15
tR
25
30
tREA tOH tREH
35
30
15
10
20
15
Aug. 09. 2005
Preliminary
-Continued-
History
Draft Date
Remark
8) Delete the errata.
9) Correct Address Cycle Map.
1) Delete the 1.8V device’s features.
2) Change DC characteristics (Table 9)
- Operating Current
I
CC1
Typ
0.3
Before
After
20
15
Max
40
30
I
CC2
Typ
20
15
Max
40
30
I
CC3
Typ
20
15
Max
40
30
Aug. 19. 2005
Preliminary
3) Correct PKG dimension (TSOP PKG)
CP
Before
After
0.4
0.050
0.100
Dec. 09. 2005
1) Delete Preliminary.
1) Correct tCS parameter in Autosleep
tCS
0.5
Before
After
100ns (Min.)
40ns (Min.)
Feb. 14. 2006
Rev 0.5 / Feb. 2006
2
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
STATUS REGISTER
ELECTRONIC SIGNATURE
- Manufacturer Code
- Device Code
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UF082G2M
- x16 device: (1K + 32 spare) Words
: HY27UF162G2M
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27UF(08/16)2G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UF(08/16)2G2M-T (Lead)
- HY27UF(08/16)2G2M-TP (Lead Free)
- HY27UF(08/16)2G2M-UP
: 52-ULGA (12 x 17 x 0.65 mm)
- HY27UF(08/16)2G2M-UP (Lead Free)
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
Memory Cell Array
: HY27UFXX2G2M
= (2K+ 64) Bytes x 64 Pages x 2,048 Blocks
= (1K+32) Words x 64 pages x 2,048 Blocks
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 30us (max.)
- Sequential access: 50ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
Rev 0.5 / Feb. 2006
3
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UF(08/16)2G2M series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UF(08/16)1G2M extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE don’t care function. This option allows the direct download of the code
from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,
Read ID2 extension.
The HYNIX HY27UF(08/16)2G2M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27UF082G2M
HY27UF162G2M
ORIZATION
x8
x16
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1 / 52-ULGA
Rev 0.5 / Feb. 2006
4
HY27UF(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
PRE
Data Input / Outputs (x16 only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Power-On Read Enable, Lock Unlock
Table 1: Signal Names
Rev 0.5 / Feb. 2006
5
stm32/stm8
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