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Two Pulse Width Modulators
- Independent Clock Rates
- 7-bit Duty Cycle Granularity
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- 4 DMA Options
- Open Drain / Push-Pull Configurable
Output Drivers
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- Software and Register Compatible with
SMC's Proprietary 82077AA Compatible
Core
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Supports Two Floppy Drives Directly
- 24 mA AT Bus Drivers
- Low Power CMOS Design
Licensed CMOS 765B Floppy Disk
Controller Core
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- 48 mA Drivers and Schmitt Trigger
Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
Enhanced Digital Data Separator
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Low Cost Implementation
No Filter Components Required
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
Multi-Mode™ Parallel Port with ChiProtect™
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- 4 DMA Options
- Enhanced Mode
- Standard Mode:
- IBM PC/XT, PC/AT, and PS/2™
Compatible Bidirectional Parallel Port
- Enhanced Parallel Port (EPP)
Compatible - EPP 1.7 and EPP 1.9
(IEEE 1284 Compliant)
- High Speed Mode
- Microsoft and Hewlett Packard
Extended Capabilities Port (ECP)
Compatible (IEEE 1284 Compliant)
- Incorporates ChiProtect™ Circuitry for
Protection Against Damage Due to
Printer Power-On
- 12 mA Output Drivers
Serial Ports
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte
FIFOs
- Programmable Baud Rate Generator
- Modem Control Circuitry Including 230K
and 460K Baud
- IrDA, HP-SIR, ASK-IR Support
208 Pin QFP/TQFP Package Options
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TABLE OF CONTENTS
GENERAL DESCRIPTION ................................ ................................ ................................ ..............1
PIN CONFIGURATION ................................ ................................ ................................ .................... 2
DESCRIPTION OF PIN FUNCTIONS ................................ ................................ .............................. 3
ALTERNATE FUNCTION PIN LIST ................................ ................................ .............................. 13
BUFFER TYPE DESCRIPTIONS ................................ ................................ ................................ ..15
FUNCTIONAL DESCRIPTION ................................ ................................ ................................ .......16
AUTO POWER MANAGEMENT ................................ ................................ ................................ ...20
FLOPPY DISK CONTROLLER ................................ ................................ ................................ .....26
FDC INSTRUCTION SET ................................ ................................ ................................ ...............53
FDC DATA TRANSFER COMMANDS ................................ ................................ .......................... 65
FDC CONTROL COMMANDS ................................ ................................ ................................ .......74
COMPATIBILITY ................................ ................................ ................................ ............................ 82
SERIAL PORT (UART) ................................ ................................ ................................ ..................85
REGISTER DESCRIPTION ................................ ................................ ................................ ............85
PROGRAMMABLE BAUD RATE GENERATOR ................................ ................................ .........95
FIFO INTERRUPT MODE OPERATION ................................ ................................ ....................... 97
FIFO POLLED MODE OPERATION ................................ ................................ ............................. 98
NOTES ON SERIAL PORT FIFO MODE OPERATION ................................ .............................. 102
INFARED COMMUNICATIONS CONTROLLER (IRCC) ................................ ............................ 105
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INTEGRATION OF IRCC LOGIC INTO ORION DEVICE ................................ ........................... 106
IRRX / IRTX PIN ENABLE ................................ ................................ ................................ ...........106
IR REGISTERS - LOGICAL DEVICE 5 ................................ ................................ ....................... 107
IR DMA CHANNELS ................................ ................................ ................................ .................... 108
IR IRQS ................................ ................................ ................................ ................................ .........108
PARALLEL PORT ................................ ................................ ................................ ........................ 109
PARALLEL PORT INTERFACE MULTIPLEXOR ................................ ................................ ......135
HOST (LEGACY) PARALLEL PORT INTERFACE (FDC37C957FR STANDARD) ..................136
PARALLEL PORT FDC INTERFACE ................................ ................................ ......................... 136
PARALLEL PORT - 8051 CONTROL (FDC37C957FR STANDARD) ................................ .......137
8051 EMBEDDED CONTROLLER ................................ ................................ .............................. 138
FEATURES ................................ ................................ ................................ ................................ ...138
8051 FUNCTIONAL OVERVIEW ................................ ................................ ................................ .138
8051 MEMORY MAP ................................ ................................ ................................ .................... 142
8051 CONTROL REGISTERS ................................ ................................ ................................ .....147
WATCH DOG TIMER ................................ ................................ ................................ ...................162
SHARED FLASH INTERFACE ................................ ................................ ................................ ....164
8051 SYSTEM POWER MANAGEMENT ................................ ................................ .................... 169
KEYBOARD CONTROLLER ................................ ................................ ................................ .......179
MAILBOX REGISTER INTERFACE ................................ ................................ ............................ 192
PS/2 INTERFACE DESCRIPTION ................................ ................................ .............................. 195
ACCESS BUS INTERFACE DESCRIPTION ................................ ................................ ..............196
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LED CONTROLS ................................ ................................ ................................ ......................... 200
PULSE WIDTH MODULATORS ................................ ................................ ................................ ..201
REAL TIME CLOCK CMOS ACCESS ................................ ................................ ........................ 202
8051 CONTROLLED PARALLEL PORT ................................ ................................ .................... 204
8051 CONTROLLED IR PORT ................................ ................................ ................................ ....207
GENERAL PURPOSE I/O (GPIO) ................................ ................................ ............................... 208
MULTIPLEXED PINS ................................ ................................ ................................ ...................214
REAL TIME CLOCK ................................ ................................ ................................ ..................... 222
VCC1 POR ................................ ................................ ................................ ................................ ....224
INTERNAL REGISTERS: ................................ ................................ ................................ ............225
TIME CALENDAR AND ALARM ................................ ................................ ................................ .226
UPDATE CYCLE ................................ ................................ ................................ .......................... 228
CONTROL AND STATUS REGISTERS ................................ ................................ ..................... 229
INTERRUPTS ................................ ................................ ................................ ............................... 233
FREQUENCY DIVIDER ................................ ................................ ................................ ................233
PERIODIC INTERRUPT SELECTION ................................ ................................ ......................... 233
POWER MANAGEMENT ................................ ................................ ................................ .............234
ACCESS BUS ................................ ................................ ................................ .............................. 236
BACKGROUND ................................ ................................ ................................ ............................ 236
REGISTER DESCRIPTION ................................ ................................ ................................ ..........236
PS/2 DEVICE INTERFACE ................................ ................................ ................................ ..........242
PS/2 LOGIC OVERVIEW ................................ ................................ ................................ .............242
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