GS842Z18/36AB-180/166/150/100
119-Bump BGA
Commercial Temp
Industrial Temp
Features
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin-compatible with 2M, 8M, and 16M devices
• 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA package
• RoHS-compliant package available
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
180 MHz–100 MHz
3.3 V V
DD
2.5 V and 3.3 V V
DDQ
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS842Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS842Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump BGA package.
Functional Description
The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
t
KQ
I
DD
t
KQ
tCycle
I
DD
–180
5.5 ns
3.2 ns
335 mA
8 ns
9.1 ns
210 mA
–166
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
–150
6.6 ns
3.8 ns
280 mA
10 ns
12 ns
165 mA
–100
10 ns
4.5 ns
190 mA
12 ns
15 ns
135 mA
Rev: 1.04c 1/2009
1/29
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS842Z18/36AB-180/166/150/100
GS842Z18A Pad Out—119-Bump BGA—Top View (Packge B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC
V
DDQ
2
A
E
2
A
NC
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
LBO
A
TDI
4
NC
ADV
V
DD
ZQ
E
1
G
NC
W
V
DD
CK
NC
CKE
A
1
A
0
V
DD
NC
TCK
5
A
A
A
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
6
A
E
3
A
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
NC
DQ
A
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Rev: 1.04c 1/2009
2/29
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS842Z18/36AB-180/166/150/100
GS842Z36A Pad Out— 119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
E
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
B
C
V
SS
NC
V
SS
B
D
V
SS
V
SS
V
SS
LBO
A
TDI
4
NC
ADV
V
DD
ZQ
E
1
G
NC
W
V
DD
CK
NC
CKE
A
1
A
0
V
DD
A
TCK
5
A
8
A
A
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
6
A
E
3
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC
NC
7
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
Rev: 1.04c 1/2009
3/29
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS842Z18/36AB-180/166/150/100
GS842Z18/36A Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
CK
CKE
W
E
1
G
ADV
ZZ
FT
LBO
ZQ
NC
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
CK
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
—
I
I
O
I
I
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
A
I/Os; active low ( x36 Version)
Clock Input Signal; active high
Clock Input Buffer Enable; active low
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active high
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
No Connect
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Clock Input Signal; active high
Rev: 1.04c 1/2009
4/29
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS842Z18/36AB-180/166/150/100
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
W
H
L
L
L
L
L
L
B
A
X
L
H
H
H
L
H
B
B
X
H
L
H
H
L
H
B
C
X
H
H
L
H
L
H
B
D
X
H
H
H
L
L
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.
Rev: 1.04c 1/2009
5/29
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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