Preliminary
GS8182Q09/18/36BD-300/250/200/167/133
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb and future 36Mb and
144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
18Mb SigmaQuad-II
Burst of 2 SRAM
300 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B2 RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read or
write transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a SigmaQuad-II B2 RAM is always one address pin
less than the advertised index depth (e.g., the 1M x 18 has a
512K addressable index).
SigmaQuad™ Family Overview
The GS8182Q09/18/36BD are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 16,777,216-bit (18Mb)
SRAMs. The GS8182Q09/18/36BD SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182Q09/18/36BD SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
Parameter Synopsis
-300
tKHKH
tKHQV
.
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
-133
7.5 ns
0.5 ns
Rev: 1.00a 6/2007
1/33
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8182Q09/18/36BD-300/250/200/167/133
Pin Description Table
Symbol
SA
NC
R
W
BW
BW0–BW3
K
K
C
C
TMS
TDI
TCK
TDO
V
REF
ZQ
Qn
Dn
D
off
CQ
CQ
V
DD
V
DDQ
V
SS
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Write
Synchronous Byte Writes
Input Clock
Input Clock
Output Clock
Output Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Synchronous Data Outputs
Synchronous Data Inputs
Disable DLL when low
Output Echo Clock
Output Echo Clock
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Supply
Supply
Supply
Comments
—
—
Active Low
Active Low
Active Low
x9 only
Active Low
x18/x36 only
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
Active Low
—
—
1.8 V Nominal
1.5 or 1.8 V Nominal
—
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V
DD
, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
Rev: 1.00a 6/2007
5/33
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
