Bus-Matching Bidirectional FIFO
512 x 18-BIT – 1,024 x 9-BIT
1,024 x 18-BIT – 2,048 x 9-BIT
IDT72510
IDT72520
NOTE: The IDT72510/72520 have been obsoleted and the last time buy will be
on 01/29/2003. These devices should not be used in new designs.
FEATURES:
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DESCRIPTION:
The IDT72510 and IDT72520 are highly integrated first-in, first-out
memories that enhance processor-to-processor and processor-to-peripheral
communications. IDT BiFIFOs integrate two side-by-side memory arrays for
data transfers in two directions.
The BiFIFOs have two ports, A and B, that both have standard micropro-
cessor interfaces. All BiFIFO operations are controlled from the 18-bit wide
Port A. The BiFIFOs incorporate bus matching logic to convert the 18-bit wide
memory data paths to the 9-bit wide Port B data bus. The BiFIFOs have a
bypass path that allows the device connected to Port A to pass messages
directly to the Port B device.
Ten registers are accessible through Port A, a Command Register, a
Status Register, and eight Configuration Registers.
The IDT BiFIFOs have programmable flags. Each FIFO memory array
has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of
eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to
any depth through the Configuration Registers. These eight internal flags can
be assigned to any of four external flag pins (FLG
A
-FLG
D
) through one
Configuration Register.
Port B has parity, reread/rewrite and DMA functions. Parity generation
and checking can be done by the BiFIFO on data passing through Port B. The
Reread and Rewrite controls will read or write Port B data blocks multiple
times. The BiFIFOs have three pins, REQ, ACK and CLK, to control DMA
transfers from Port B devices.
Two side-by-side FIFO memory arrays for bidirectional data
transfers
512 x 18-Bit – 1,024 x 9-Bit (IDT72510)
1,024 x 18-Bit – 2,048 x 9-Bit (IDT72520)
18-bit data bus on Port A side and 9-bit data bus on Port B side
Can be configured for 18-to-9-bit, 36-to-9-bit, or 36-to-18-bit
communication
Fast 25ns access time
Fully programmable standard microprocessor interface
Built-in bypass path for direct data transfer between two ports
Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
Two programmable flags, Almost-Empty and Almost-Full for
each FIFO
Programmable flag offset can be set to any depth in the FIFO
Any of the eight internal flags can be assigned to four external
flag pins
Flexible reread/rewrite capabilities
On-chip parity checking and generation
Standard DMA control pins for data exchange with
peripherals
IDT72510 and IDT72520 available in the the 52-pin PLCC
package
Industrial temperature range (–40°C to +85°C) is available
°
°
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
18-bits
Data
Bypass Path
9-bits
9-bits
Data
Port
A
18-Bit
FIFO
Port
B
Registers
Control
Processor
Interface
A
Processor
Interface
B
Control
Flags
Programmable
Flag Logic
Handshake
Interface
DMA
2669 drw 01
FEBRUARY 2002
1
©
2002 Integrated Device Technology, Inc.
DSC-2669/2
IDT72510/72520
Commercial Temperature Range
PIN CONFIGURATION
LDREW
D
A8
LDRER
GND
GND
D
A16
D
A9
DS
A
V
CC
INDEX
7 6 5 4 3 2
D
A10
D
A11
D
A12
D
A13
D
A14
D
A15
D
A17
A
0
A
1
FLG
D
FLG
C
FLG
B
FLG
A
8
9
10
11
12
13
14
15
16
17
18
19
20
1
52 51 50 49 48 47
46
45
44
43
42
41
40
39
38
37
36
35
34
D
A4
D
A3
D
A2
D
A1
D
A0
CS
A
R/W
A
RER
REW
REQ
ACK
CLK
D
B0
21 22 23 24 25 26 27 28 29 30 31 32 33
V
CC
W
B
(R/W
B
)
GND
GND
D
B8
D
B7
D
B6
D
B5
R
B
(DS
B
)
D
B4
D
B3
D
B2
D
B1
2669 drw 02
PLCC (J52-1, order code: J)
TOP VIEW
2
D
A7
D
A6
D
A5
RS
IDT72510/72520
Commercial Temperature Range
PIN DESCRIPTIONS
Symbol
DA0-DA15
DA16-DA17
CSA
DSA
R/WA
Name
Data A
Parity A
Chip Select A
Data Strobe A
Read/Write A
I/O
I/O
I/O
I
I
I
Description
Data inputs and outputs for 16 bits of the 18-bit Port A bus.
DA16 is the parity bit for DA0-DA7. DA17 is the parity bit for DA8-DA15. DA16 and DA17 can be used as two extra
data bits if the parity generate function is disabled.
Port A is accessed when Chip Select A is LOW.
Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the
falling edge of Data Strobe when Chip Select A is LOW.
This pin controls the read or write direction of Port A. When
CSA
is LOW and R/WA is HIGH, data is read from Port A
on the falling edge of
DSA.
When
CSA
is LOW and R/WA is LOW, data is written into Port A on the rising edge of
DSA.
When Chip Select A is asserted, A0, A1, and Read/Write A are used to select one of six internal resources.
Data inputs and outputs for 8 bits of the 9-bit Port B bus.
DB8 is the parity bit for DB0-DB7. DB8 can be used as a data bit if the parity generate function is disabled.
If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode
this pin functions as an output. This pin can function as part of an Intel-style interface (RB) or as part of a Motorola-style
interface (DSB). As an Intel-style interface, data is read from Port B on a falling edge of
RB.
As a Motorola-style
interface, data is read on the falling edge of
DSB
or written on the rising edge of
DSB
through Port B. The Default is Intel-
style processor mode (RB as an input).
If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode
this pin functions as an output. This pin can function as part of an Intel-style interface (WB) or as part of a Motorola-style
interface (R/WB). As an Intel style interface, data is written to Port B on a rising edge of
WB.
As a Motorola-style
interface, data is read (R/WB = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B falling or
rising edge. The Default is Intel-style processor mode (WB as input).
Loads A-to-B FIFO Read Pointer with the value of the Reread Pointer when LOW.
Loads B-to-A FIFO Write Pointer with the value of the Rewrite Pointer when LOW.
Loads the Reread Pointer with the value of the A-to-B FIFO Read Pointer when HIGH. This signal is accessible
through the Command Register.
Loads the Rewrite Pointer with the value of the B-to-A FIFO Write Pointer when HIGH. This signal is accessible
through the Command Register.
When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed
either active HIGH or active LOW.
When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request signal. This
confirms that a data transfer may begin. Acknowledge can be programmed either active HIGH or active LOW.
This pin is used to generate timing for ACK,
RB, WB, DSB
and R/WB when Port B is in the peripheral mode.
These four outputs pins can be assigned to any one of the eight internal flags in the BiFIFO. Each of the two internal
FIFOs (A-to-B and B-to-A) has four internal flags: Empty, Almost-Empty, Almost-Full, and Full. If parity checking is
enabled, the FLGA pin can also be assigned as a parity error output.
A LOW on this pin will perform a reset of all BiFIFO functions. Software reset can be achieved through command
register.
There are two +5V power pins on all four devices.
There are four ground pins
2669 tbl 01
A0, A1
DB0-DB7
DB8
RB
(DSB)
Addresses
Data B
Parity B
Read B
I
I/O
I/O
I or O
WB
(R/WB)
Write B
I or O
RER
REW
LDRER
LDREW
REQ
ACK
CLK
FLGA-FLGD
Reread
Rewrite
Load Reread
Load Rewrite
Request
Acknowledge
Clock
Flags
I
I
I
I
I
O
I
O
RS
V
CC
GND
Reset
Power
Ground
I
3
ReRead Pointer
Load Reread
Reread
Read Pointer
Write Pointer
IDT72510/72520
CS
A
DS
A
R/W
A
A
1
A
0
Port A
Control
A
Parity Bit 17
Parity Bit 16
(D
B8
)
MUX
B FIFO
Port B
Control
LDRER
LDREW
RER
REW
R
B
(DS
B
)
W
B
(R/W
B
)
Data Bits 8-15
18
Data Bits 0-7
Bypass Path
(D
B0-
DB
7
)
8
9
MUX
1
8
Port A
DETAILED BLOCK DIAGRAM
D
A0
-
D
A17
Parity
Generate/
Check
8
Read Parity Error
(D
A0
-D
A7
,D
A16
)
Port B
D
B0
-
D
B8
Parity
Generate/
Check
B
Parity Bit 17
Parity Bit 16
9
Data Bits 8-15
Odd Byte
Register
A FIFO
8
18
Data Bits 0-7
Reset
RS
4
Read Pointer
Load Rewrite
Command
Status
Configuration 0
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
ReWrite Pointer
Rewrite
Write Pointer
Write
Parity Error
DMA
Control
REQ*
ACK*
CLK
16
(D
A0
-D
A15
)
FLG
A*
FLG
B*
FLG
C*
FLG
D*
Programmable
Flag Logic
Commercial Temperature Range
2669 drw 03
NOTES:
(*) Can be programmed either active high or active low in internal configuration registers.
( ) Accessible through internal registers.
( ) Can be programmed through an internal configuration register to be either an input or an output.
IDT72510/72520
Commercial Temperature Range
18- to 9-bit Configurations
A single BiFIFO can be configured to connect an 18-bit processor to
another 9-bit processor or a 9-bit peripheral. Bits 11 and 12 of Configuration
Register 5 should be set to
00
for a stand-alone configuration. Figures 1 and
2 show the BiFIFO in 18- to 9-bit configurations for processor and peripheral
interface modes respectively.
36- to 9-bit Configurations
Two BiFIFOs can be hooked together to create a 36-bit to 9-bit
configuration. This means that a 36-bit processor can talk to a 9-bit
processor or a 9-bit peripheral. Both BiFIFOs are programmed simultane-
ously through Port A by placing one command word on the most signifi-
cant 16 data bits and one command word on the least significant 16 data
bits (parity bits should be ignored).
One BiFIFO must be programmed as the master device and the other
BiFIFO is the slave device. Bits 11 and 12 of Configuration Register 5 are
set to
10
for the slave device and
11
for the master device. The first two 9-
bit words on Port B are read from or written to the slave device and the
next two 9-bit words go to the master device.
When both BiFIFOs are in peripheral interface mode, the Port B
interface pins of the master device are outputs and this BiFIFO controls
the bus. The Port B interface pins of the slave device are inputs driven by
the master BiFIFO. Two BiFIFOs are connected in Figure 4 to create a 36-
to 9-bit peripheral interface.
FUNCTIONAL DESCRIPTION
IDT’s BiFIFO family is versatile for both multiprocessor and peripheral
applications. Data can be sent through both FIFO memories concurrently,
thus freeing both processors from laborious direct memory access (DMA)
protocols and frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the IDT BiFIFO, making
simultaneous data exchange possible. Each FIFO is monitored by separate
internal read and write pointers, so communication is not only bidirectional, it
is also totally independent in each direction. The processor connected to Port
A of the BiFIFO can send or receive messages directly to the Port B device
using the BiFIFO’s 9-bit bypass path.
The BiFIFOs can be used in three different bus configurations: 18 bits
to 9 bits, 36 bits to 9 bits and 36 bits to 18 bits. One BiFIFO can be used
for the 18- to 9-bit configuration, and two BiFIFOs are required for 36- to 9-
bit or 36- to 18-bit configurations. Bits 11 and 12 of Configuration Register
5 determine the BiFIFO configuration (see Table 11 for Configuration Register
5 format).
The microprocessor or microcontroller connected to Port A controls all
operations of the BiFIFOs. Thus, all Port A interface pins are inputs driven
by the controlling processor.
Port B can be programmed to interface either with a second processor or
a peripheral device. When Port B is programmed in processor interface
mode, the Port B interface pins are inputs driven by the second processor. If
a peripheral device is connected to the BiFIFOs, Port B is programmed to
peripheral interface mode and the interface pins are outputs.
36-BIT PROCESSOR TO 18-BIT PROCESSOR CONFIGURATION
IDT
BiFIFO
(Stand-Alone)
Cntl A Cntl B
ACK
REQ
CLK
Data A Data B
Control
Logic
Address
Control
Control
Logic
Processor
A
Processor
B
Control
36-bit bus
Data
36
18-bit bus
Data
18
IDT
BiFIFO
(Stand-Alone)
Cntl A Cntl B
ACK
REQ
CLK
Data A Data B
18
9
RAM
RAM
2669 drw 04
NOTE:
1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that
Cntl A
refers to
CS
A,
A
1
, A
0
, R/W
A a
nd
DS
A;
Cntl B
refers to R/W
B
and
DS
B
or
R
B
and
W
B
.
Figure 1. 36- to 18-Bit Processor Interface Configuration
5
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