HDV24
ADP II
SRAM
eo
3.3 Volt x16 Asynchronous Dual-Port Static RAM
Memory Configuration
4K x 16
Device
HDV24
Key Features:
•
•
•
•
•
•
•
•
•
Industry leading Dual-Port Static RAM (up to 15ns)
Simultaneous memory access through two ports
LVTTL compatible; 3.3V power supply
Easily expands bus width to 32 bits or more using the MASTER/SLAVE select function
Supports Busy, Interrupt and Semaphore arbitration schemes
Available packages: 100 – pin Thin Quad Flat Pack (TQFP) and 84 – pin Plastic Lead Chip Carrier (PLCC)
(0
°
C to 70
°
C) Commercial operating temperature available for access time of 15ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for access time of 25ns
Pin-to-pin compatible with conventional dual-port devices including IDT (70V24) and Cypress (CY7C024AV)
Product Description:
The HDV24 Dual-Port Static RAM offers industry leading 0.25um process technology and 4K x 16 memory configuration. The
device supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access
to any location in memory. System designer has full flexibility of implementing deeper and wider memory using the depth and
width expansion features.
The HDV24 is a stand alone 64K-bit Dual-Port SRAM or as a MASTER/SLAVE combination Dual Port SRAM. The
MASTER/SLAVE approach in 32 or more bit application offers bus width expansion without additional discrete logic.
These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such
as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.
3HD166A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to
change without notice.
PRELIMINARY
Page 1 of 18
HDV24
ADP II
SRAM
Block Diagram of Dual Port Static RAM
4K x 16
R/ W
L
UB
L
R/ W
R
UB
R
L B
L
LB
R
C E
R
OE
L
CE
L
OE
R
I/O
8-15
L
I/O
Control
I/O
0-7
L
I/O
Control
I/O
8-15
R
I/O
0-7
R
BUSY
L
BUSY
R
A
11
L
A
0
L
Address
Decoder
SRAM
Address
Decoder
A
11
R
A
0
R
CE
L
OE
L
R/ W
L
SEM
INT
Arbitration
Interrupt
Semaphore
Logic
CE
R
OE
R
R/ W
R
SEM
L
L
R
M/ S
__________
__________
INT
R
Note: MASTER mode: BUSY is output. SLAVE mode: BUSY is input
Figure 1. Device Architecture
3HD166A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to
change without notice.
PRELIMINARY
Page 2 of 18
HDV24
ADP II
SRAM
SEM
L
CE
L
VCC
R/W
L
I/O
2L
GND
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
1L
I/O
0L
A
11L
A
10L
UB
L
LB
L
OE
L
A
9L
A
8L
79
78
Index
100 99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
77
76
75
74
73
72
71
70
69
68
67
66
A
7L
A
6L
NC
NC
NC
NC
NC
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
VCC
GND
I/O
0R
I/O
1R
I/O
2R
VCC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
TQFP-100
(Drw No: PF-04A; Order Code: PF)
Top View
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LB
R
NC
A
9R
A
8R
A
7R
A
8L
75
A
6R
A
11R
GND
R/W
R
GND
SEM
R
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
SEM
L
CE
L
VCC
R/W
L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
UB
L
LB
L
NC
A
11L
A
10R
OE
R
CE
R
UB
R
A
10L
OE
L
Index
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
A
9L
76
A
5R
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
VCC
GND
I/O
0R
I/O
1R
I/O
2R
VCC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
74
73
72
71
70
69
68
67
PLCC-84
(Drw No: J-03A; Order Code: J)
Top View
66
65
64
63
62
61
60
59
58
57
56
55
54
NC
A
11R
A
10R
I/O
14R
GND
I/O
15R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
OE
R
R/W
R
GND
I/O
9R
Figure 2. Device Pin-Out
SEM
R
CE
R
UB
R
LB
R
A
9R
A
8R
A
7R
3HD166A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to
change without notice.
PRELIMINARY
Page 3 of 18
HDV24
ADP II
SRAM
Left Port
______
Right Port
______
Name
Chip Enable
Read / Write Enable
Output Enable
Address
Data Inputs / Outputs
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
Symbol
Rating
Terminal Voltage with
respect to GND
Temperature Under Bias
Storage Temperature
DC Output Current
Com & Ind
-0.5 to + 4.6
-55 to +125
-65 to +150
50
Unit
V
°
C E
L
____
C E
R
____
R/W
L
OE
L
A
0L-11L
I/O
0L – 15L
SEM
L
______
_____
________
_____
R/W
R
OE
R
A
0R-11R
I/O
0R – 15R
SEM
R
______
_____
________
_____
V
TERM
T
BIAS
T
STG
I
OUT
NOTES:
C
C
°
mA
UB
L
LB
L
UB
R
LB
R
BUSY
L
__________
INT
L
______
M/ S
Vcc
___
BUSY
R
__________
INT
R
______
Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended
period of operation is outside this range. Standard operation should fall within the Recommended
Operating Conditions
.
Table 2. Absolute Maximum Ratings
GND
Table 1. Pin Descriptions
Symbol
Parameter
Commercial Temperature
Min.
3.0
0
2.0
-
0
-
-
2.4
-
Industrial Temperature
Min.
3.0
0
2.0
-
-40
-
-
2.4
-
Typ.
3.3
0
-
-
-
-
-
-
-
Max.
3.6
0
-
0.8
70
10
10
-
0.4
Typ.
3.3
0
-
-
-
-
-
-
-
Max.
3.6
0
-
0.8
85
10
10
-
0.4
Unit
Recommended Operating Conditions
V
CC
GND
Supply Voltage Com’l/Ind’l
Supply Voltage
Input High Voltage Com’l/Ind’l
Input Low Voltage Com’l/Ind’l
Operating Temperature
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, IOH=-4mA
Output Logic “0” Voltage, IOL = 4mA
V
V
V
V
°
V
IH
V
IL
T
A
I
LI
(1)
I
LO
V
OH
V
OL
C
DC Electrical Characteristics
µA
µA
V
V
Capacitance at 1.0MHz Ambient Temperature (25°C)
Symbol
Parameter
Input Capacitance
C
IN(2)
Output Capacitance
C
OUT(2)
NOTES:
Conditions
(3)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
11
Unit
pF
pF
1. At Vcc < 2.0V, input leakage is undefined.
2. This parameter is determined by device characterization but is not production tested.
3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V.
3HD166A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to
change without notice.
PRELIMINARY
Page 4 of 18
HDV24
ADP II
SRAM
Power Consumption
Symbol
Parameter
Dynamic
Operating
Current (Both
Ports Active)
Standby Current
(Both Ports –
TTL Level
Inputs)
Standby Current
(One Port – TTL
Level Inputs)
Full Standby
Current (Both
Ports – All
CMOS Level
Inputs)
Standby Current
(One Port – All
CMOS Level
Inputs)
_____
Conditions
Outputs
CE = V
IL
,
________
Disabled, SEM = V
IH
,
f=f
MAX
(1)
CE
L
= CE
R
= V
IH
,
________
________
SEM
R
= SEM
L
= V
IH
,
f=f
MAX
(1)
CE
A
= V
IL
and CE
B
=
V
IH
Active Port Outputs
Disabled, f=f
MAX
(1)
_____
Both Ports CE
L
and
_____
CE
R
> Vcc – 0.2V,
V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
(2)
,
________
________
SEM
R
= SEM
L
> Vcc
– 0.2V
_____
_____
CE
A
< 0.2V and CE
B
________
> Vcc – 0.2V, SEM
R
________
= SEM
L
> Vcc –
0.2V, Active Port
Outputs Disabled,
f=f
MAX
(1)
_____
_____
_____
_____
Temp
C
I
C
I
C
I
C
HDV24L15
Typ.
140
-
20
-
80
-
0.2
HDV24L25
Typ.
125
125
13
13
72
72
0.2
HDV24L35
Typ.
115
-
11
-
65
-
0.2
Unit
Max.
185
-
30
-
110
-
2.5
Max.
165
180
25
40
95
110
2.5
Max.
155
-
20
-
90
-
2.5
mA
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
C
-
80
-
105
0.2
70
5
90
-
60
-
85
mA
I
SB4
I
-
-
70
105
-
-
NOTES:
1. At f = f
MAX
, address and I/O’s are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC Test Conditions” of input levels of GND to 3V.
2. f = 0: no control and address bits change.
3HD166A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to
change without notice.
PRELIMINARY
Page 5 of 18
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