AT91SAM ARM-based Flash MCU
SAM7L128/SAM7L64
DATASHEET
Description
The AT91SAM7L128/64 are low power members of Atmel’s Smart ARM Microcontroller family based on the 32-
bit ARM7
™
RISC processor and high-speed Flash memory.
• AT91SAM7L128 features a 128 Kbyte high-speed Flash and a total of 6 Kbytes SRAM.
• AT91SAM7L64 features a 64 Kbyte high-speed Flash and a total of 6 Kbytes SRAM.
They also embed a large set of peripherals, including a Segment LCD Controller and a complete set of system
functions minimizing the number of external components.
These devices provide an ideal migration path for 8-bit microcontroller users looking for additional performance,
extended memory and higher levels of system integration with strong constraints on power consumption.
Featuring innovative power reduction modes and ultra-low-power operation, the AT91SAM7L128/64 is tailored
for battery operated applications such as calculators, toys, remote controls, medical devices, mobile phone
accessories and wireless sensors.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel inter-
face on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from
accidental overwrite and preserve its confidentiality.
The AT91SAM7L128/64 system controller includes a reset controller capable of managing the power-on
sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-
in brownout detector and a watchdog running off an integrated oscillator.
By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral func-
tions, including USART, SPI, External Bus Timer Counter, RTC and Analog-to-Digital Converters on a
monolithic chip, the AT91SAM7L128/64 microcontroller is a powerful device that provides a flexible, cost-effec-
tive solution to many embedded control applications.
6257B–ATARM–01-Feb-13
1. Features
•
Incorporates the ARM7TDMI
®
ARM
®
Thumb
®
Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
™
In-circuit Emulation, Debug Communication Channel Support
Internal High-speed Flash
– 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane
– 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane
– Single Cycle Access at Up to 15 MHz in Worst Case Conditions
– 128-bit Read Access
– Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time: 10 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 6 Kbytes
• 2 Kbytes Directly on Main Supply That Can Be Used as Backup SRAM
• 4 Kbytes in the Core
Memory Controller (MC)
– Enhanced Embedded Flash Controller, Abort Status and Misalignment Detection
Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
Reset Controller (RSTC)
– Based on Zero-power Power-on Reset and Fully Programmble Brownout Detector
– Provides External Reset Signal Shaping and Reset Source Status
Clock Generator (CKGR)
– Low-power 32 kHz RC Oscillator, 32 kHz On-chip Oscillator, 2 MHz Fast RC Oscillator and one PLL
Supply Controller (SUPC)
– Minimizes Device Power Consumption
– Manages the Different Supplies On Chip
– Supports Multiple Wake-up Sources
Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Active and Four Low Power Modes:
• Idle Mode: No Processor Clock
• Wait Mode: No Processor Clock, Voltage Regulator Output at Minimum
• Backup Mode: Voltage Regulator and Processor Switched Off
• Off (Power Down) Mode: Entire Chip Shut Down Except for Force Wake Up Pin (FWUP) that Re-activates the Device.
100 nA Current Consumption.
In Active Mode, Dynamic Power Consumption <30 mA at 36 MHz
– Three Programmable External Clock Signals
– Handles Fast Start Up
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– Two-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention
Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
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SAM7L128/64 [DATASHEET]
6257B–ATARM–01-Feb-13
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Windowed Watchdog (WDT)
– 12-bit Key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter may be Stopped While the Processor is in Debug State or in Idle Mode
Real-time Clock (RTC)
– Two Hundred Year Calendar with Alarm
– Runs Off the Internal RC or Crystal Oscillator
Three Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– Eighty Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
Eleven Peripheral DMA Controller (PDC) Channels
One Segment LCD Controller
– Display Capacity of Forty Segments and Ten Common Terminals
– Software Selectable LCD Output Voltage (Contrast)
Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA
®
Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Manchester Encoder/Decoder
– Full Modem Line Support on USART1
One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 16-bit PWM Controller (PWMC)
One Two-wire Interface (TWI)
– Master, Multi-Master and Slave Mode Support, All Atmel
®
Two-wire EEPROMs and I
2
C compatible Devices Supported
– General Call Supported in Slave Mode
One 4-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
SAM-BA
®
Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
– In Application Programming Function (IAP)
IEEE
®
1149.1 JTAG Boundary Scan on All Digital Pins
Four High-current Drive I/O lines, Up to 4 mA Each
Power Supplies
– Embedded 1.8V Regulator, Drawing up to 60 mA for the Core with Programmable Output Voltage
– Single Supply 1.8V - 3.6V
Fully Static Operation: Up to 36 MHz at 85⋅ C, Worst Case Conditions
Available in a 128-lead LQFP Green and a 144-ball LFBGA Green Package
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SAM7L128/64 [DATASHEET]
6257B–ATARM–01-Feb-13
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2. Block Diagram
Figure 2-1.
AT91SAM7L128/64 Block Diagram
TDI
TDO
TMS
TCK
JTAGSEL
JTAG
SCAN
ICE
ARM7TDMI
Processor
Charge
Pump
CAPP1
CAPM1
CAPP2
CAPM2
VDDINLCD
VDD3V6
VDDLCD
VDDIO2
System Controller
TST
FIQ
PIO
2 MHz RCOSC
LCD
Voltage
Regulator
1.8 V
Voltage
Regulator
IRQ0-IRQ1
AIC
VDDIO1
GND
VDDOUT
VDDCORE
PCK0-PCK2
CLKIN
PLLRC
XIN
XOUT
Memory Controller
PLL
OSC
32k RCOSC
VDDIO2
PMC
Embedded
Flash
Controller
Abort
Status
SRAM
2 Kbytes( Back-up)
4 Kbytes (Core)
Address
Decoder
Misalignment
Detection
VDDCORE
VDDIO1
BOD
POR
Supply
Controller
Peripheral Bridge
Flash
64/128 Kbytes
ERASE
VDDIO1
NRST
NRSTB
FWUP
Peripheral Data
Controller
11 Channels
VDDIO1
ROM
(12 Kbytes)
Fast Flash
Programming
Interface
APB
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
PGMD0-PGMD15
PGMNCMD
PGMEN0-PGMEN2
SAM-BA
RTC
PIT
WDT
DRXD
DTXD
PIO
DBGU
PDC
PDC
PWMC
Timer Counter
TC0
TC1
TC2
PDC
PIOA (26 IOs)
PIOB (24 IOs)
PIOC (30 IOs)
PWM0
PWM1
PWM2
PWM3
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TWI
PIO
TWD
TWCK
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
ADTRG
AD0
AD1
AD2
AD3
ADVREF
SEG00-SEG39
COM0-COM9
LCD Controller
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
PDC
PDC
PDC
SPI
USART0
PIO
PDC
PDC
PDC
PDC
ADC
USART1
PDC
SAM7L128/64 [DATASHEET]
6257B–ATARM–01-Feb-13
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3. Signal Description
Table 3-1.
Signal Name
Signal Description List
Function
Type
Power
Active
Level
Voltage
Reference Comments
VDDIO1
VDDOUT
VDDCORE
VDDINLCD
VDD3V6
VDDLCD
I/O Lines (PIOC) and Voltage Regulator
Power Supply
Voltage Regulator Output
Core Power Supply
Charge Pump Power Supply
Charge Pump Output
LCD Voltage Regulator Power Supply
LCD Voltage Regulator Output
and
LCD I/O Lines Power Supply (PIOA and
PIOB)
Charge pump capacitor 1
Charge pump capacitor 1
Charge pump capacitor 2
Charge pump capacitor 2
Force Wake-up
Wake-up inputs used in Backup mode and
Fast Start-up inputs in Wait mode
Ground
Power
Power
Power
Power
Power
Power
From 1.80V to 3.6V
Connected externally to VDDOUT
From 1.80V to 3.6V
VDDIO2
Power
1.80V to 3.6V
CAPP1
CAPM1
CAPP2
CAPM2
FWUP
WKUP0-15
GND
Power
Power
Power
Power
Input
Input
Ground
Clocks, Oscillators and PLLs
Low
VDDIO1
VDDIO1
Capacitor needed between CAPP1
and CAPM1.
Capacitor needed between CAPP2
and CAPM2.
Needs external Pull-up.
XIN
XOUT
CLKIN
PCK0 - PCK2
PLLRC
PLLRCGND
32 kHz Oscillator Input
32 kHz Oscillator Output
Main Clock input
Programmable Clock Output
PLL Filter
PLL RC Filter Ground
Input
Output
Input
Output
Input
Power
ICE and JTAG
VDDIO1
VDDIO1
VDDIO1
Should be tied low when not used.
VDDCORE
Must not be connected to external
Ground.
TCK
TDI
TDO
TMS
JTAGSEL
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
Input
Input
Output
Input
Input
Flash Memory
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
No internal pull-up resistor
No internal pull-up resistor
No internal pull-up resistor
Internal Pull-down resistor
ERASE
Flash and NVM Configuration Bits Erase
Command
Input
High
VDDIO1
Internal Pull-down (15 k
Ω
) resistor
SAM7L128/64 [DATASHEET]
6257B–ATARM–01-Feb-13
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