SAM4C Series
Atmel | SMART ARM-based Flash MCU
DATASHEET
Description
The Atmel
®
| SMART SAM4C microcontrollers are system-on-chip solutions for
smart energy applications, built around two high-performance 32-bit ARM
®
Cortex
®
-M4 RISC processors.
These devices operate at a maximum speed of 120 MHz and feature up to
2 Mbytes of embedded Flash, up to 304 Kbytes of SRAM and on-chip cache for
each core.
The dual ARM Cortex-M4 architecture allows for integration of an application
layer, communications layers and security functions in a single device, with the
ability to extend program and data memory via a 16-bit external bus interface.
The peripheral set includes advanced cryptographic engine, anti-tamper, floating
point unit (FPU), USB Full-speed Host/Device port, five USARTs, two UARTs, two
TWIs, up to seven SPIs, as well as a PWM timer, two 3-channel general-purpose
16-bit timers, calibrated low-power RTC running on the backup domain down
to 0.5 µA, and a 50 × 6 segmented LCD controller.
The SAM4C series is a scalable platform providing, alongside Atmel's industry
leading SAM4 standard microcontrollers, unprecedented cost structure,
performance and flexibility to smart meter designers worldwide.
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
Features
Application/Master Core
̶
̶
̶
̶
̶
̶
ARM Cortex-M4 running at up to 120 MHz
(1)
Memory Protection Unit (MPU)
DSP Instruction
Thumb
®
-2 instruction set
Instruction and Data Cache Controller with 2 Kbytes Cache Memory
Memories
Up to 2 Mbytes of Embedded Flash for Program Code (I-Code bus) and Program Data (D-Code bus)
with Built-in ECC (2-bit error detection and 1-bit correction per 128 bits)
Up to
256 Kbytes of Embedded SRAM (SRAM0) for Program Data (System bus)
8 Kbytes of ROM with embedded bootloader routines (UART) and In-Application Programming (IAP)
routines
Coprocessor (provides ability to separate application, communication or metrology functions)
̶
̶
̶
̶
̶
̶
ARM Cortex-M4F running at up to 120 MHz
(1)
IEEE
®
754 Compliant, Single-precision Floating-Point Unit (FPU)
DSP Instruction
Thumb-2 instruction set
Instruction and Data Cache Controller with 2 Kbytes of Cache Memory
Memories
Up to
32 Kbytes of Embedded SRAM (SRAM1) for Program Code (I-Code bus) and Program Data
(D-Code bus and System bus)
Up to
16 Kbytes of Embedded SRAM (SRAM2) for Program Data (System bus)
Symmetrical/Asynchronous Dual Core Architecture
̶
̶
̶
̶
Interrupt-based Interprocessor Communication
Asynchronous Clocking
One Interrupt Controller (NVIC) for each core
Each Peripheral IRQ routed to each NVIC Input
̶
̶
̶
̶
High-performance AES 128 to 256 with various modes (GCM, CBC, ECB, CFB, CBC-MAC, CTR)
TRNG (up to 38 Mbit/s stream, with tested Diehard and FIPS)
Public Key Crypto accelerator and associated ROM library for RSA, ECC, DSA, ECDSA
Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256),
DMA-assisted
̶
̶
Up to four physical Anti-tamper Detection I/Os with Time Stamping and Immediate Clear of General
Backup Registers
Security Bit for Device Protection from JTAG Accesses
̶
Power Supply
Embedded core and LCD voltage regulator for single-supply operation
Power-on-Reset (POR), Brownout Detector (BOD) and Dual Watchdog for safe operation
Ultra-low-power Backup mode (< 0.5 µA Typical @ 25°C)
Cryptography
Safety
Shared System Controller
2
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
̶
Clock
Optional 3 to 20 MHz quartz or ceramic resonator oscillators with clock failure detection
Ultra-low-power 32.768 kHz crystal oscillator for RTC with frequency monitoring
High-precision 4/8/12 MHz factory-trimmed internal RC oscillator with on-the-fly trimming capability
One high-frequency PLL up to 240 MHz, one 8 MHz PLL with internal 32 kHz input, as source for
high-frequency PLL
Low-power slow clock internal RC oscillator as permanent clock
̶
̶
Ultra-low-power RTC with Gregorian and Persian Calendar, Waveform Generation in Low-power
modes and Clock Calibration Circuitry for 32.768 kHz Crystal Frequency Compensation Circuitry
Up to 23 Peripheral DMA (PDC) Channels
̶
One Segmented LCD Controller
Display capacity of 50 segments and 6 common terminals
Software-selectable LCD output voltage (Contrast)
Low current consumption in Low-power mode
Can be used in Backup mode
Up to five USARTs with ISO7816, IrDA
®
, RS-485, SPI and Manchester Mode
Two 2-wire UARTs with one UART (UART1) supporting optical transceiver providing an electrically
isolated serial communication with hand-held equipment, such as calibrators, compliant with ANSI-
C12.18 or IEC62056-21 norms
Shared Peripherals
̶
̶
̶
̶
̶
̶
̶
̶
̶
Full-speed USB Host and Device Port (available only for SAM4C32E in a 144-pin package)
Two 400 kHz Master/Slave and Multi-Master Two-wire Interfaces (I
2
C compatible)
Up to seven Serial Peripheral Interfaces (SPI)
Two 3-channel 16-bit Timer/Counters with Capture, Waveform, Compare and PWM modes
Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
4-channel 16-bit Pulse Width Modulator
32-bit Real-time Timer
̶
̶
̶
8-channel, 500 kS/s, Low-power 10-bit SAR ADC with Digital Averager providing 12-bit Resolution
at 30 kS/s
Software-controlled On-chip Reference ranging from 1.6V to 3.4V
Temperature Sensor and Backup Battery Voltage Measurement Channel
̶
̶
Star Topology AHB-AP Debug Access Port Implementation with Common SW-DP / SWJ-DP Providing
Higher Performance than Daisy-chain Topology
Debug Synchronization between both Cores (cross triggering to/from each core for Halt and Run
Mode)
̶
Up to
106 I/O lines with External Interrupt Capability (edge or level sensitivity), Schmitt Trigger,
Internal Pull-up/pull-down, Debouncing, Glitch Filtering and On-die Series Resistor Termination
̶
̶
100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
144-lead LQFP, 20 x 20 mm, pitch 0.5 mm (SAM4C32E only)
1. 120 MHz: -40°C/+85°C, VDDCORE = 1.2V
Analog Conversion Block
Debug
I/O
Packages
Note:
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
3
1.
Configuration Summary
The SAM4C devices differ in memory size, package and features.
Table 1-1
summarizes the SAM4C device
configurations.
Table 1-1.
Flash
SRAM
Package
Configuration Summary
SAM4C32E
2048 Kbytes
256 + 32 + 16 Kbytes
LQFP 144
106
SAM4C32C
2048 Kbytes
256 + 32 + 16 Kbytes
LQFP 100
74
16-bit data
6 channels
4 channels
2/5
2/5 + 5
2
8
AES, CPKCC, ICM (SHA), TRNG
50 segments × 6 commons
4
512 bytes
2 × 2048
8 Kbytes
256 (128 + 128)
128
64
2048
1024
SAM4C16C
1024 Kbytes
128 + 16 + 8 Kbytes
LQFP 100
74
SAM4C8C
512 Kbytes
128 + 16 + 8 Kbytes
LQFP 100
74
Feature
Number of PIOs
External Bus Interface
16-bit Timer
16-bit PWM
UART/USART
SPI
(1)
TWI
10-bit ADC Channels
(2)
Cryptography
Segmented LCD
Anti-Tampering Inputs
Flash Page Size
Flash Pages
Flash Lock Region Size
Flash Lock Bits
Notes:
1. 2/5 + 5 = Number of SPI Controllers / Number of Chip Selects + Number of USARTs with SPI mode.
2. One channel is reserved for internal temperature sensor and one channel for VDDBU measurement.
4
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
2.
Block Diagram
SAM4C16/8 100-pin Block Diagram
TD
TDI
TMO/T
R
TC S/S AC
K/ WD ES
SW IO W
O
CL
K
TST
PCK0-PCK2
VDDPLL
Figure 2-1.
System Controller
PLLA
8 MHz
PLLB
High Freq.
RC OSC
4/8/12 MHz
PMC
Instr./Data
Cache
Controller
2 Kb
Cache
Memory
Serial Wire and JTAG Debug Port (SW-DP/SWJ-DP)
ICM (SHA)
(Integrity
Check Module)
AHB-AP
AHB-AP
JT
AG
SE
L
WKUP[0:15]
XIN
XOUT
VDDBU
VDDIO
XTAL OSC
3 - 20 MHz
Automatic
Power Switch
Peripheral
DMA 0
DMA
Cortex-M4
CM4P0
ICode / DCode bus
MPU
DSP
N
V
I
C
Cortex-M4F
CM4P1
ICode / DCode bus
DSP
FPU
N
V
I
C
Instr./Data
Cache
Controller
2 Kb
Cache
Memory
Peripheral
DMA 1
System bus
System bus
Backup Zone
XOUT32
XIN32
ERASE
SHDN
WKUP[0:15]
FWUP
RTCOUT0
XTAL OSC
32 kHz
RC 32 kHz
Supply
Controller
Real-time Clock
Time Stamping
Slave
Master
Master/Slave
Master
Master
Master
Master
Master
Master/Slave
Master
High Speed AHB Multilayer Bus Matrix 0
Slave
Slave
Slave
Slave
Slave
Slave/Master
High Speed AHB Multilayer Bus Matrix 1
Slave/Master Slave
Slave
Slave
Slave
Backup Reg (16)
TMP[1:3]
TMP0
VDDCORE
Real-Time Timer
S Bus
Anti-tampering
Flash
1024/512 Kb
ROM
(SAM-BA
CPKCL)
SRAM 0
128 Kb
CPKCC
(Classical Public Key
Cryptography
Controller )
Asynchronous
AHB to AHB
Bridge
S Bus
I/D Bus
AHB to APB
Bridge 1
SRAM 2
8 Kb
PDC1
SRAM 1
16 Kb
SPI1_NPCS[0:3]
SPI1_MISO1
SPI1_MOSI1
SPCK1
UTXD1
ECC
Supp.Mon POR
NRST
Reset
Controller
SPI1
PIO Controller
Dual Watchdog
VDDOUT
VDDIN
VDDLCD
AHB to APB
Bridge 0
PDC1
UART1
Optical Port
PWM
Interprocessor
Communication
(IPC1)
URXD1
Core Voltage
Regulator
LCD Voltage
Regulator
TWI0
PWM[0:3]
TWCK0
TWD0
TWCK1
TWD1
URXD0
UTXD0
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
RXD2
TXD2
SCK2
RTS2
CTS2
RXD3
TXD3
SCK3
RTS3
CTS3
RXD4
TXD4
SCK4
RTS4
CTS4
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
TCLK[3:5]
TIOA[3:5]
TIOB[3:5]
PDC0
TWI1
UART0
PDC0
External Bus
Interface
PIO
SAM4C16/8C
LQFP100
Static Memory
Controller 1
NAND Flash
Logic
USART0
PDC0
USART1
PDC0
Static Memory
Controller 0
NAND Flash
Logic
D[15:0]
A[23:0]
NANDALE
NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
USART2
PDC0
VDDLCD
USART3
PDC0
Interprocessor
Communication
(IPC0)
Segment LCD
Controller
PDC0
COM[0..5]
SEG[0..49]
USART4
PDC0
Timer Counter A
TC[0..2]
PDC0
Timer Counter B
TC[3..5]
Temp. Sensor
ADVREF
ADTRG
AD[0..5]
True Random
Number Generator
10-bit ADC
Digital Averager
PDC0
AES
SPI0
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPCK0
Sub-system 0
Sub-system 1
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
