One 600–1200 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed
̶
Internal Low-power 12 MHz RC Oscillator
̶
Low-power 32 kHz RC Oscillator
̶
Selectable 32768 Hz Low-power oscillator and 12 MHz Oscillator
̶
Two 64-bit, 16-channel DMA Controller
̶
64-bit Advanced Interrupt Controller
̶
64-bit Secure Advanced Interrupt Controller
̶
Three Programmable External Clock Signals
̶
Programmable fuse box with 512 fuse bits available for customer, including JTAG protection
Peripherals
̶
Video Decoder (VDEC) supporting formats MPEG-4, H.264, H.263, VP8 and JPEG, and image postprocessing
̶
LCD TFT Controller with 4 overlays up to 2048x2048 or up to 720p in video format, with rotation and alpha
blending
̶
ITU-R BT. 601/656 Image Sensor Interface (ISI)
̶
One USB Device High-Speed, Three USB Host High-Speed with On-chip Transceiver
̶
Two 10/100 Mbps Ethernet MAC Controllers with IEEE 1588 v2 support
̶
SoftModem Interface (SMD)
̶
Two high-speed memory card hosts (eMMC 4.3 and SD 2.0)
̶
Three Master/Slave Serial Peripheral Interfaces (SPI)
̶
Five USARTs, two UARTs, one DBGU
̶
Two Synchronous Serial Controllers (SSC)
̶
Four Two-wire Interfaces up to 400 Kbits/s supporting I2C protocol and SMBUS (TWI)
̶
Three 3-channel 32-bit Timer/Counters (TC)
̶
One 4-channel 16-bit PWM Controller
̶
One 5-channel 10-bit Analog-to-Digital Converter with Resistive Touchscreen function
2
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
Safety
̶
Internal and external memory integrity monitoring (Integrity Check Monitor based on SHA256)
̶
Power-on Reset Cells
̶
Main Crystal Clock Failure Detector
̶
Independent Watchdog
̶
Register Write Protection
̶
Memory Management Unit
Security
̶
512 bits of scrambled and erasable registers
̶
8 Kbytes of internal scrambled RAM with non-imprinting support, 6 Kbytes are erasable
̶
8 PIOBU tamper pins for static or dynamic intrusion detections
(1)
̶
Atmel secure boot
(2)
Cryptography
̶
True Random Number Generator (TRNG)
̶
SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512) compliant with FIPS
publications 180-2
̶
AES: 256-bit, 192-bit, 128-bit Key Algorithm, compliant with FIPS PUB 197 specifications
̶
TDES: Two-key or Three-key Algorithms, compliant with FIPS PUB 46-3 specifications
̶
Public Key Coprocessor (CPKCC) and associated Classical Public Key Cryptography Library (CPKCL) for RSA,
DSA, ECC GF(2
n
), ECC GF(p)
(3)
Up to 152 I/Os
̶
Five Parallel Input/Output Controllers with slew rate control on high-speed I/Os
̶
Input Change Interrupt capability on each I/O Line, selectable Schmitt Trigger input
̶
Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering
Packages
̶
361-ball stubless BGA, 16x16 mm body, pitch 0.8 mm
̶
289-ball stubless BGA, 14x14 mm body, pitch 0.8 mm
SAMA5D4 Series Devices
Device
SAMA5D44
SAMA5D43
SAMA5D42
SAMA5D41
Package
BGA361
BGA289
BGA361
BGA289
Video Decoder
X
X
–
–
DDR Datapath
32 bits
16 bits
32 bits
16 bits
Table 1-1.
1.
2.
3.
Intrusion detection is described in the document “Secure Box Module (SBM)”, Atmel literature No. 11254. This document is available under Non-Disclosure
Agreement (NDA). Contact an Atmel Sales Representative for further details.
For secure boot strategies, refer to the application note “SAMA5D4x Secure Boot Strategy”, Atmel literature No. 11295. This document is available under Non-
Disclosure Agreement (NDA). Contact an Atmel Sales Representative for further details.
CPKCC and CPKCL are described in the application note "Using CPKCL Version 02.05.01.xx on SAMA5D4", Atmel literature No. 11214. This document is
available under Non-Disclosure Agreement (NDA). Contact an Atmel Sales Representative for further details.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
3
2.
Figure 2-1.
LP
CA
DR
_
D
D
DR
_
CA
LN
NT
RS
T
T
DI
TD
O
TM
TC S/SW
K/S D
W IO
JTA
CLK
GS
EL
PLLA
JTAG / SWD
PC
GMAC0
GMAC1
10/100
Video
Decoder
LCD
ISI
DMA
DMA
DMA
DMA
PB
PA
PLLUTMI
PIO
PIO
HH
S
HH DP
SD C
HH
MC
H S
H SD P B
VB
D M
G
B
HS
Trans
HS
Trans
HS
Trans
DH
S
DH DP
SD /HH
M/ S
HH DPA
G
SD
x_
MA
Gx
TXC
_
K
Gx TXE
–G
_
N–
x_R
G C
x_ RS– Gx_
XCK
Gx RXD Gx TX
_
V _ C ER
Gx RX , G OL
_ [0: x_
Gx
TX[ 3] RX
ER
0
G _M
:3
x_ DC
]
MD
IO
L
CD
LC DA
D T[
L
_ 0
CD
VSY :23]
LC
_PC
NC
,
D
_D
K, L
LC
EN
CD
D_
,LC
_D
HS
IS
D_
ISP
YNC
I_
PW
IS D[0
I_ :1
M
I
V 1
SI
SY ]
_P
NC
CK
, I
,
IS
SI_H
I_M
S
CK
YNC
PIO
Cyphering
4
DDR_A0–DDR_A13
DDR_D0–DDR_D31
DDR_DQM[3..0]
DDR_DQS[3..0]
TST
Block Diagram
XIN
XOUT
In-Circuit Emulator
Trust
Zone
OSC12M
PLL12M
PCK0–PCK2
PMC
Cortex-A5
MMU
32 KB
DCache
DMA
DMA
NEON
FPU
HS EHCI
USB HOST
HS USB
Device
WDT
32 KB
ICache
128 KB L2 Cache
Secured EBI
PIT
SAMA5D4 Series [DATASHEET]
DDR2
LPDDR
LPDDR2
512 MB
DDR_DQSN[3..0]
DDR_CS
DDR_CLK, DDR_CLKN
DDR_CKE
DDR_RAS, DDR_CAS
DDR_WE
DDR_BA[2..0]
FIQ
SAIC
SAMA5D4 Series Block Diagram
DRXD
PIO
Scrambling
POR
VDDBU
XIN32
XOUT32
32K OSC
64K RC
SHDN
RTC
WKUP
SHDC
ROM
128 KB
CPKCC
SHA
SRAM
128 KB
TRNG
16-CH
DMA0
AES
TDES
Peripheral
Bridge 0
ICM
(SHA)
Peripheral
Bridge 1
16-CH
DMA1
Reduced
Static
Memory
Controller
PIO
Scrambling
DI
BP
P
W
DIB
PWMH
N
[3
PW ML :0]
M [3:0
F
I[ ]
TI
1:0
O
]
TI A[5
O :0
TC B[5 ]
LK :0]
[5
TW
:0]
TW
D[
CK
3:0
[3
]
:
CT
0]
S
R
[4
T
:0]
SC
S[4
:0
RX K[4
]
D :0]
TX
[4:
D[
0]
UR
4:0
]
X
UT D[1
XD :0]
NP
[1:0
CS
]
[3
SP :0]
C
M K
O
M SI
IS
O
TK
TF[1:0
TD[1: ]
0
R [1 ]
D[ :0]
RF 1:0
[ ]
R 1
K[ :0]
1:
M
0]
CI
x
M M _C
C C D
M I0 Ix A
CI _D _C
0_ A[ K
D 7.
M MC B[3 .0]
CI I0 ..
1_ _C 0]
D
A[ DB
3.
.0
]
AD
VR
AD EF
T
A R
D[ IG
0:
4]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
I/D
IRQ
AIC
DTXD
DBGU
VDDCORE
POR
Fuse Box
NRST
Trustzone Secured Multi-Layer Matrix
NAND Flash
Controller
MCL/SLC
ECC
(4KB SRAM)
RSTC
D0–D15
A21/NANDALE
A22/NANDCLE
NRD/NANDOE
NWE/NWR0/NANDWE
NCS3/NANDCS
NANDRDY
A0/NBS0
A1–A20
A23–A25
NWR1/NBS1
NCS0, NCS1, NCS2
NWAIT
PIOBU[7..0]
SECURAM
8 KB
+
512 bits
SMD
4-CH
PWM
TC0,TC1
TC2,TC3
TC4,TC5
TC6,
TC7, TC8
TWI0
TWI1
TWI2
TWI3
USART0
USART1
USART2
USART3
USART4
UART0
UART1
SPI0
SPI1
SPI2
SSC0
SSC1
MCI0/MCI1
SD/SDIO
eMMC
5-CH
10-bit ADC
Touchscreen
PIO
PIO
PIO
SPI0_,
SPI1_,
SPI2_
Legend
Trustzone Access Right Management
xxx
xxx
xxx
Always Secured
Programmable Secured (PS)
Secured and Non-Secured
3.
Signal Description
Table 3-1
gives details on signal names classified by peripheral.