P'"
JIG
7 {()
F
7
ANALOG
8-, 10-,12-Bit
Video
Speed
W DEVICES Current ndVoltage
a
Out,D
/
A
Converters
FEA TURES
Current Settling Times to 15ns
:t1.5V Compliance
Voltage Settling Times to 100ns (MDH)
Monotonicity Guaranteed Over Temperature
15mA
High Output Currents
-30°C to +85°C Operating Range
Industry Standard Pin Outs
20V, p.p Out (MDH)
TTl
or
ECl logic
,.
-
OBS
APPLICATIONS
CRT Vector Displays
Digitial Waveform Generation
Automatic Test Equipment
TV Picture Reconstruction
FULL
SCALE
MODEL
MDS-0815
MDS-I020
MDS-1240
MDS-O815E
MDS-I020E
MDSL-0825
MDSL-I035
MDSL-1250
MDH-0870
MDH-l00l
MDH-1202
BITS
8
to
12
8
10
8
10
12
8
10
12
OUTPUT
GENERAL DESCRIPTION
This broad family
of
digital-to-analog converters represents the
"state
of
the art" in modular, high speed, voltage and current
output devices. The family consists
of
a total
of
11 devices in
4 series (MDS, MDSE, MDSL and MDH) that allow the user to
make engineering trade-offs between resolution, speed, output
and logic type. The first 3 are high compliance current output
unitS which make possible linear output swings greater than
:t1.5V. The voltage output MDH series contain a fast settling
hybrid operational amplifier which provides:t 10V output at
:t5OmA. To simplify selection these major specifications are
summarized in Table 1.
FULL SCALE
SETTLING TIME
OLE
TE
INPUT
LOGIC
TTL
TTL
TTL
ECL
ECL
TTL
TTL
TTL
TTL
TTL
TTL
achieve ultra-high speed operation. In fact, it is the fastest 12-
bit D/A available, settling to 0.025% in 40ns. Hybrid construc-
tion eliminates the thermal lag problem inherent in 12-bit
D/A's constructed with discrete componentS. This in turn
means that the accuracy is maintained over the total frequency
range of operation, yielding superior results for frequency do-
main applications.
(Fastest Settling High Current Out)
15mA
15ns to 0.4% FS
15mA
20n5 to 0.1% FS
15mA
40n5 to 0.025% FS
(MDS with ECL Logic)
15mA
15ns to 0.4% FS
15mA
20n5 to 0.1% FS
(Low Current MDS)
SmA
25n5toO.l%
SmA
25n5toO.l%
SmA
SOns to 0.025%
(Voltage Out MDSL)
10V /50mA
150n5 to 0.4%
,tOV/50mA
200n5 to 0,1 %
tOV /50mA
500n5 to 0.025%
Table
The MDS-1240 is particularly well suited for CRT display ap-
plications because
of
its unsurpassed speed and drive capa-
bilities. The high output current (ISmA) allows the use of low
impedance loads so that settling times remain short - even
with higher output voltage levels. The ability to drive load ca-
pacitance is at least 3 times that of other 12-bit D/A's thus
providing capability to drive a terminated transmission line
directly. The MDS-815 and MDS-I020 provide similar per-
formance at 8 and 10 bits, while the MDS-E units provide it
with ECL logic. MDSL-082S, MDSL-I035 and MDSL-12S0
also utilize this reliable hybrid construction. The use
of
laser
trimmed resistor networks within the D/A's not only elimi-
nates thermal time lag errors but provide the linearity temp-
co of 2ppmtC; guaranteeing monotonic operation over the
extended temperature range of -30°C to +8SoC. The power
dissipation of the MDSL series is one-half that of competi-
tive D/A's, but a full SmA output current is maintained. This
allows driving transmission lines or other low impedance loads
directly.
(continued
on page 1955)
1.
SPEED WITH PRECISION
Analog Devices' model MDS-1240 is the first D/A converter
available with highly reliable, internal hybrid construction to
Page 1 of 8
D/A
CONVERTERS 1915
',:-",~,,"",
,'C
,:C°';'"
-:",
~",;:",,":_'.,-:
:-"
"".':_-"_:'.~,':,,-:.:.c'-,
',',:'
<,:'"",..:,~.~,,':".,':<""",-,;",.,::,,:,::;,.:,.',,',:,,':;:":'.-:.'
,;,:'
",:"',',",
SPECIFICATIONS
@+25°C unlessotherwisespecified)
(typical
MODEL
RESOLUTION
LSB (Weight)
ACCURACY
Initial (Adjust to 0)
Linearity (Integral)
Monotonicity
UNITS
Bits
IlA
:!:%FS
LSB max
CURRENT OUTPUT
MDS
0815
1020
8
58.6
0.2
:!:li2
10
14.6
0.05
1240
12
3.66
0.012
CURRENT OUTPUT
MDS-E (ECL)
0815
1020
8
58.6
0.2
10
14.6
0.05
.
.
Zero Offset (Adjust to 0)
TEMPERATURECOEFFICIENTS
Gain
Guaranteed Over Operating Temp Range
'
ISnA max
.
.
'
.
.
.
.
2
Linearity
ppm/C
5
OBS
DATA INPUTS
Logic Comparability
Logic Voltage Levels
Offset (ipolar)
STABILITY WITH TIME
30
ppm/C
15
ppm/C
:!:%/yrmax 0.5
TTL
+2 to +5.0
0 to +0.4
.
.
"
'
.
.
.
.
.
.
2
20
.
.
.
.
ECL
.
.
.
ECL
BitOnLogic"I"
Bit Off Logic "0"
LogicCurrent (Each Bit)
BitOnLogic"I"
Bit Off Logic"0"
V
V
JlA
Coding
MSB
mA
mA
OUTPUT
Current Range
Unipolar
Bipolar
Impedance
mA
mA
3)
(See Figure
n
V
Compliance (MDH VOUT)
Load Resistance for VOUT (See Figure 5)
Oro+lV
:!:IV
n
n
V
INTERNAL EFERENCE OLTAGE UT
R
V
O
SETTLING TIME2
Current
Unipolar
Bipolar
Voltage
Voltage
(RL
(RL
OLE
TE
';;;50
'
-0.9
-1.7
-0.9
-1.7
-8
N/A
.
.
.
.
-10max
-5max
All Units Binary(BIN) for Unipolar,
Offset Binary (OBN) for Bipolar
Oto+15
.
.
.
.
.
.
.
.
.
.
:!:7.5
165
112
+1.5,-2
4.32k
N/A
.
.
.
.
'
.
.
.
Oto-15
'
'
200:!: 1%
-1.5, +2
100
750
-6.2 :!:5%
.
.
.
.
'
-1.5, +2
.
.
.
.
.
0 to -15
ns to %.
IS to 0.4
20 to 0.10
20 to 0.1
40 to 0.025
'
20 to 0.10
=
300n
II 10pF)
III0pF)
ns to %
ns to %
=
2325n
POWER REQUIREMENTS
Range
Current at Nominal +V
V
:!:11to :tl6
'
Current at Nominal-V
POWER SUPPLY REJECTION RATIO
+15V
-15V (Bipolar)
-15V (Unipolar)
TEMPERATURE RANGE
Operating
mA max
mA max
%/V
"la/V
%/V
%/V
°c
105
IS
0.04
.
'
'
:!:14.5 to :!:16.5
120
55
20
-0.0001
-0.002
-0.2
.
.
.
.
'
.
.
.
.
120
-20 to +75
Storage
CASE
PRICE
(1-4)
.Specifications
NOTES,
same as
MDS~81S.
°c
-55 to +85
'
-30 to +85
-55 to +125
'
Diallyl Phthalate per MIL-M-14 Type SDG-F
$
lIS
137
149
'
129
.
.
149
1 Ippmt' C for current output, Op amp is SOllY /° C. (See tables in Figures
for overall TC in various configurations.)
'For Full Scale Step.
15. 16 and 17,
'0 to +5V Out
'0 to +10V Out
See Figures 15 and 16 for test circuits.
'tSV
Out
f
Specifications subject to change without notice,
Page 2 of 8
1925 D/A CONVERTERS
MDS-o815, 0815E, 1020, 1020E
OUTLINE DIMENSIONS
Dimensions
shown L'1inches and (rom).
2.3 (58.01
MD5-1240, MDSL-O825, 1035, 1250
OUTLINE DIMENSIONS
Dimensions
shown in inches and (mm).
MDH-o870, 1001, 1202
OUTLINE DIMENSIONS
Dimensions
shown in inches and (mm).
2.0
150.8)
---j
--L
0.'
110.2)
:t"
r
.L
Lo.25(...,
3>1
2.0""I.8)---1i
MOH.(J870
MOH.'OO'.
MOH.I202
MO"""
MOS-'O2O
MOS-CIO'" MOS-'...'
1-
0.0411.0210IA
0.43
"o.")
+
mil
I
.L
MOS.'2..
MOSL<l825
MOSL.'035
MOSL.""
G.02 10.508)
0.'
110.2'
0.02
10.508)
~
3
t1
'°
L."
23
;58.01
0.25
(OA)
.L
I
BOTTOM
VIEW
DOT
ON
TOP
_II
-,
INDICATES
WiIIl
r-°.'
12.54IGRIO
OF PIN
POSITION
T
DOT
OBS
,.
_J
a++++IIIIIIII1
:
.
16
OOTTOMVIEW
-11-0.'1254'GRI0
ON
TOP
INDICATES
FOSITION
321 I I I I I I I I I I I I II I. I
I 1 I I 1 I
1 1 I I
1
I
1
2.0
7
'°
(50.8)
0.25
16.4'
2.0
(50..'
I
.L
,.
.-
j
OOTTOMVIEW
-11-
0.1(254)
GRID
OF PIN ,.
OOT ON TOP INDICATES POSITION OF PIN ,.
MATING SOCKET MSA-l
MATING
SOCKET MSA-1
MATING SOCKET MSB-11713
PIN DESIGNATIONS
MDS-o81 5E, 1020E
FUNCTION
BIT 1 (MSB)
BIT 2
BIT 3
BIT4
BIT5
BIT6
BIT 7
BIT 8
PIN
9
10
11
12
13
14
15
16
PIN
1
2
3
4
5
6
7
8
FUNCTION
BIT 9
BIT 10
+15V
OFFSET
COMMON
OUTPUT
COMMON
-15V
1",581
BIT 1
BIT2
BIT3
BIT4
BITS
BIT6
BIT7
BITS
BIT9
BIT 10
(lSBI
OLE
TE
PIN
1
2
3
4
5
6
7
8
FUNCTION
BIT 1(MSBI
BIT 2
BIT3
BIT 4
BIT5
BIT 6
BIT7
BIT8
PIN
9
10
11
12
13
14
15
16
FUNCTION
BIT9
BIT 10
-15V
OFFSET
COMMON
OUTPUT
COMMON
+15V
PIN
3
4
5
6
7
10
11
12
13
14
FUNCTION
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
1 INPUT (MSBI
2 INPUT
3 INPUT
4 INPUT
5 INPUT
6 INPUT
7 INPUT
8 INPUT
9 INPUT
10 INPUT
PIN
15
16
17
18
28
29
30
31
32
PIN DESIGNATIONS
MD5-0815, MDS-I020
PIN DESIGNATIONS
MDS-1240, MDSL-O825, 1035, 1250
FUNCTION
BIT 11 INPUT
BIT 12 INPUT
REFERENCE INPUT
REFERENCE OUTPUT
ANALOG OUTPUT
OFFSET
GROUND
-15V POWER INPUT
+15V POWER INPUT
PIN DESIGNATIONS
MDH-o870, 1001, 1202
PIN
17
18
22
24
25
26
28
29
30
31
32
14
---COUTPUT
12
DIGITAL
INPUTS
OFFSET
COMMON
COMMON
PIN
3
4
5
6
7
10
11
12
13
14
15
16
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
FUNCTION
1 INPUT (MSB)
2 INPUT
3 INPUT
4 INPUT
5 INPUT
6 INPUT
7 INPUT
8 INPUT
9 INPUT
10 INPUT
11 INPUT
12 INPUT
FUNCTION
REFERENCE IfIIPUT
REFERENCE OUTPUT
ANALOG OUTPUT
+INPUT
-INPUT
FIXED GAIN
CURRENT OUTPUT
OFFSET
GROUND
-15V POWER INPUT
+15V POWER INPUT
MDS and MDSE
Block Diagram
(M581
BIT 1
BIT2
BIT 3
Zo
-soon
'"
3.16k
HYBRID
CURRENT
OUTPUT
DIA
CONVERTER
-SMA F.S.
gT
24 - +IN
22
";8;
tlOV (MAX)
'SOMA (MAXI
25
DIGITAL
INPUTS
MSB
BIT 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
BIT 12
lSB
GROUND
CURRENT
OUTPUT
HYBRID
CURRENT
OUTPUT
DIA
CONVERTER
BIT4
BITS
BIT6
BIT7
BIT 8
BIT9
- -IN
OFFSET
BIT 10
BIT 11
FIXED
GAIN
+ISV
BIT 12
ILSBI
REFINe
10 to ~.2V-
0 TO SMA
OUTPUT'
17
Z,N
= 4.641<
OFFSET
+ISV
-ISV
~ISV
18
REF
OUT
REF OUT
IS
eND
MDS-1240 and MDSL Series
Block
Diagram
Page 4 of 8
MDH
Series
Block Diagram
1945 D/A CONVERTERS
"-,-"""""-""-~'-",,,,,,",,"--
MDH SERIES APPLICATIONS
By using external feedback resistor and capacitor as shown
in Figures 15 and 16, other full scale output ranges from 2V
to 10V may be obtained.
+1SV
MAVBE
OMITTED
USE INVERTER OR
FF aFaR 2'S COMPL.
1', DIGITAL INPUTS
.
}
MSB
BIT 1
I
I
I
I
I
I
I
I
I
I
I
BIT 12
LSB
MSB
I' -.
..."
20011
OFFSET ADJ
29 _OFFSET
,,!
4
'5
24
+INPUT
DIGITIAL
INPUTS
MDH
DIA
CONVERTER
.
OUTPUT CURRENT ISEE BELOWI
Vo
UP TO
10V
>6OmA
DIGITAL
INPUTS
fT
i
'7
soon
30 - ~~DDUTPUT
}
FS ADJ
ll
NOTES'
BIT 12
LSB
I
I
I
I
ill
ill
12
i3
i4
is
ii
~~::
CONVERTER
-16V
+1SV
3. FOR TWO'S COMPLEMENT
12SC! OPERATION,
AN EXTERNAL
INVERTER
MUST BE USED TO
COMPLEMENT
BIT 1IMSBI-
4. AN ADJUSTABLE
CAPACITOR
MAV BE USED
FOR C AND ADJUSTED
TO OPTIMIZE SET-
TLING TIME.
OBS
-16V
+16V
NOTES'
1. VALUE OF C IS APPROXIMATE.
A FIXED
CAPACITOR
WITH TOLERANCE
OF >1pF MAV
BE USED IF 601< DEGRADATION
OF SETTLING
TIME IS PERMITTED
IF SETTLING TIME IS
TO BE OPTIMIZED,AN
ADJUSTABLE
CAPACI-
TOR SHOULD BE USED FOR C AND ADJUSTED
FOR MINIMUM SETTLING
TIME.
2. OFFSET NULLING MAV BE ACCOMPLISHED
BV
CONNECTING
A 1Ok POTENTIOMETER
BETWEEN
+16V
AND
-16V,
AND CONNECTING
ITS ADJUST-
ABLE T;.p TO A 1Ok RESISTOR.
THE OTHER END
OF THE RESISTOR
IS CONNECTED
TO PIN 2B.
TVPICAL UNCOMPENSATED
OFFSET
IS '" OF
FULL SCALE.
1. Tho 200n POTENTIOMETER
IS ADJUSTED
FOR AN CUTPUT OF -FS WITH ALL ZEROES
IN THE DIGITAL INPUT.
2. THE soon POTENTIOMETER
IS ADJUSTED
FOR AN OUTPUT OF +F5-1LSB
WITH ALL
ONE'S IN THE DIGITAL INPUT.
VOLTAGE
OUTPUT
SETTLING
TIME
70ns
lOOns
200ns
OFFSET
TEMPCO
lOOV/C
250vfc
500V!'C
0 to +2V
0 to +5V
Oto+lOV
Figure
15.
Binary Coding Unipolar Output
OLE
TE
R
C
VOLTAGE
OUTPUT
SETTLING
TIME
OFFSET
TEMPCO
2k
8k
18k
10pF
2pF
0.5pF
:tlV
:t2V
:t5V
:tlOV
70ns
lOOns
lOOns
200ns
100V
fc
200V /C
250vfc
500vfc
RL
383
383
9.1k
9.1k
C
lOpF
2pF
2pF
0.5pF
Configuration
R
2k
6k
8k
18k
Figure
16.
Offset Binary Coding or
2'$
Comp Coding
Bipolar Output Configuration
Page 5 of 8
19B5 DIA CONVERTERS
嵌入式系统
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