Preliminary
Datasheet
Specifications in this document are tentative and subject to
RZ/T1 Group
R01DS0228EJ0070
Rev.0.70
Dec 25, 2014
450 MHz/600MHz, MCU with ARM Cortex
®
-R4F and -M3*
1
, on-chip FPU, 747/996 DMIPS, up to 1
Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*
1
, USB 2.0 high-speed, CAN, various
communications interfaces such as an SPI multi-I/O bus controller,
∆Σ
interface, safety functions,
encoder interfaces*
1
, and security functions*
1
Features
■
On-chip 32-bit ARM Cortex-R4F processor
High-speed realtime control with maximum operating frequency of
450/600 MHz
Capable of 747/996 DMIPS (in operation at 450/600 MHz)
On-chip 32-bit ARM Cortex-R4F (revision r1p4)
Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes
Instruction cache/data cache with ECC: 8 Kbytes per cache
High-speed interrupt
The FPU supports addition, subtraction, multiplication, division,
multiply-and-accumulate, and square-root operations at single-
precision and double-precision.
Harvard architecture with 8-stage pipeline
Supports the memory protection unit (MPU)
ARM CoreSight architecture, includes support for debugging
through JTAG and SWD interfaces
PRBG0320GA-A 17×17mm, 0.8-mm pitch
PLQP0176LD-A 20 x 20mm, 0.4-mm pitch
■
On-chip 32-bit ARM Cortex-M3 processor
(in products incorporating an R-IN engine)
150-MHz operating frequency
On-chip 32-bit ARM Cortex-M3 (revision r2p1)
RISC Harvard architecture with 3-stage pipeline
Supports the memory protection unit (MPU)
Standby mode, sleep mode, and module stop function
Up to 1 Mbyte of the on-chip extended SRAM with ECC
150 MHz
DMAC: 16 channels × 2 units
DMAC for the Ethernet controller: 1 channel
Module operations can be started by event signals rather than by
interrupt handlers.
Linked operation of modules is available even while the CPU is in
the sleep state.
Four reset sources including a pin reset
Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V
(internal)
External clock/oscillator input frequency: 25 MHz
CPU clock frequency: Up to 450/600 MHz
Low-speed on-chip oscillator (LOCO): 240 kHz
Operated by a clock signal obtained by frequency-dividing the
clock signal from the low-speed on-chip oscillator: Up to 120 kHz
Register write protection, input clock oscillation stop detection,
CRC, IWDTa, and A/D self-diagnosis
An error control module is incorporated to generate a pin signal
output, interrupt, or internal reset in response to errors originating
in the various modules.
Boot mode with security through encryption
EnDat 2.2 and BiSS-compliant interfaces
■
Various communications interfaces
Ethernet
- EtherCAT slave controller: 2 ports (for products incorporating an
R-IN engine)
- Ether-MAC: 1 port (without the switching function)
or
- Ether-MAC: 1 port (2 ports with the switching function)
USB 2.0 high-speed host/function : 1 channel
CAN (compliant with ISO11898-1): 2 channels (max.)
SCIFA with 16-byte transmission and reception FIFOs: 5 channels
I
2
C bus interface: 2 channels for transfer at up to 400 kbps
RSPIa: 4 channels
SPIBSC: Provides a single interface for multi-I/O
compatible
■
Low power consumption
■
On-chip extended SRAM
■
Data transfer
■
Event link controller
serial flash memory
■
External address space
Buses for high-speed data transfer at 75 MHz (max.)
Support for up to 6 CS areas
8-, 16-, or 32-bit bus space is selectable per area
16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4
channels): Input capture, output compare, PWM waveform output
16-bit CMT (6 channels), 32-bit CMTW (2 channels)
■
Up to 33 extended-function timers
■
Reset and power supply voltage control
■
Serial sound interface (1 channel)
■ ∆Σ
interface
Up to 4
ΔΣ
modulators are connectable externally.
12 bits × 2 units (max.)
(8 channels for unit 0; 16 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
■
Clock functions
■
12-bit A/D converters
■
Independent watchdog timer
■
Safety functions
■
Temperature sensor for measuring temperature
within the chip
■
General-purpose I/O ports
5-V tolerance, open drain, input pull-up
The locations of input/output functions for peripheral modules are
selectable from among multiple pins.
Tj = -40°C to +125°C
Tj: Junction temperature
■
Multi-function pin controller
■
Operating temperature range
■
Security functions (optional)*
2
■
Encoder interfaces (optional)*
3
Note 1.
Note 2.
Note 3.
Optional
Details of these optional functions will only be given after completion of a binding non-disclosure agreement. For details, contact our sales
representative.
For details, contact our sales representative.
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 1 of 52
Under development
RZ/T1 Group
Preliminary document
Specifications in this document are tentative and subject to change.
1. Overview
1.
1.1
Overview
Outline of Specifications
This LSI circuit is a high-performance MCU equipped with the ARM Cortex
®
-R4F processor and Cortex-M3 (for
products incorporating an R-IN engine) processors, and incorporating integrated peripheral functions necessary for
system configuration.
Table 1.1
lists the specifications in outline, and
Table 1.2
gives a comparison of the functions of
products in different packages.
Table 1.1
shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package. For details, see
Table 1.2,
Comparison of Functions for Different
Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1 / 7)
Module/Function
Central processing unit
(Cortex-R4F)
Description
Maximum operating frequency
320-pin FBGA: 600 MHz
176-pin HLQFP: 450 MHz
32-bit CPU Cortex-R4F designed by ARM (core revision r1p4)
Address space: 4 Gbytes
Instruction cache: 8 Kbytes (with ECC with)
Data cache: 8 Kbytes (with ECC with)
Tightly coupled memory (TCM)
ATCM: 512 Kbytes (with ECC with)
BTCM: 32 Kbytes (with ECC with)
Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2
Data arrangement
Instructions: Little endian
Data: Little endian
Memory protection unit (MPU)
Operating frequency: 150 MHz
32-bit CPU Cortex-M3 designed by ARM (core revision r2p1)
Address space: 4 Gbytes
Instruction set: ARMv7-R architecture, so support includes Thumb® and Thumb-2
Data arrangement
Instructions: Little endian
Data: Little endian
Memory protection unit (MPU)
Supports addition, subtraction, multiplication, division, multiply-and-accumulate, and
square-root operations at single- and double-precision.
Registers
32-bit single-word registers: 32 bits ×32
(can be used as 16 double-word registers: 64 bits x 16)
Capacity: Up to 1 Mbyte
150 MHz
SEC-DED (single error correction/double error detection)
Three boot modes
SPI boot mode (for booting up from serial flash memory)
16-bit bus boot mode (NOR Flash)
32-bit bus boot mode (NOR Flash)
Clock generation circuit
The input clock can be selected from an external clock signal or external resonator.
Detection of input clock oscillation stopping
The following clocks are generated.
CPU clock: 450/600 MHz (max.)
System clock: 150 MHz (fixed)
High-speed peripheral module clock: 150 MHz (fixed)
Low-speed peripheral module clock: 75 MHz (fixed)
ADCCLK in the 12-bit A/D converter (S12ADC): 60 MHz (max.)
External bus clock: 75 MHz (max.)
Low-speed on-chip oscillator: 240 kHz (fixed)
RES # pin reset, error control module (ECM) reset, software reset
Central processing unit
(Cortex-M3)
(for products
incorporating an R-IN
engine)
FPU
(Cortex-R4F)
Memory
On-chip extended
SRAM with ECC
Operating modes
Clock
Reset
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 2 of 52
Under development
RZ/T1 Group
Table 1.1
Classification
Low power
Preliminary document
Specifications in this document are tentative and subject to change.
1. Overview
Outline of Specifications (2 / 7)
Module/Function
Low power consumption
Description
Standby mode (Cortex-R4F)
Sleep mode (Cortex-M3) (for products incorporating an R-IN engine)
Module stop function
Peripheral function interrupts: 272 sources / 274 sources (for products incorporating an
R-IN engine)
External interrupts: 20 sources
(NMI, IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)
Software interrupts: 1 source
Non-maskable interrupts: 2 sources
Sixteen levels specifiable for the order of priority
Peripheral function interrupts: 82 sources
External interrupts: 19 sources
(IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)
Software interrupts: 1 source
Non-maskable interrupts: 1 source
Sixteen levels specifiable for the order of priority
The external address space is divided into six areas (CS0 to CS5) for management.
The following features settable for each area independently.
Bus size (8, 16, or 32 bits): Available sizes depend on the area.
Number of access wait cycles (different wait cycles can be specified for read and write
access cycles in some areas)
Idle wait cycle insertion (between same area access cycles or different area access
cycles)
Specifying the memory to be connected to each area enables direct connection to
SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or
asynchronous). The address/data multiplexed I/O (MPX) interface is also available.
Outputs a chip select signal (CS0# to CS5#) according to the target area (CS assert or
negate timing can be selected by software)
SDRAM refresh
Auto refresh or self-refresh mode selectable
SDRAM burst access
2 units (16 channels for unit 0, 16 channels for unit 1)
Transfer modes: Single transfer mode and block transfer mode
Transfer size
Unit 0: 1/2/4/16/32/64 bytes
Unit 1: 1/2/4/16 bytes
Activation sources: Software trigger, external DMA requests (DREQ0 to DREQ2),
external interrupts, and interrupt requests from peripheral functions
320-pin FBGA
I/O pins: 209
Input pins: 9
Pull-up/pull-down resistors: 209
Open-drain outputs: 9
5-V tolerance: 9
176-pin HLQFP
I/O pins: 97
Input pins: 5
Pull-up/pull-down resistors: 97
Open-drain outputs: 5
5-V tolerance: 5
87 event signals can be interlinked with the operation of modules.
In particular, the operation of timer modules can be started by input event signals.
Event-linked operation of signals of ports B and E is to be possible.
The locations of input/output functions are selectable from among multiple pins.
Interrupt
Cortex-R4F
vector interrupt
controller (VIC)
Cortex-M3 nested-type
vector interrupt
controller (NVIC)
(only included in
products incorporating
an R-IN engine)
External bus
extension
Bus state controller
(BSC)
Data transfer
Direct memory access
controller (DMAC)
I/O ports
General-purpose I/O
ports
Event link controller (ELC)
Multi-function pin controller (MPC)
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 3 of 52
Under development
RZ/T1 Group
Table 1.1
Classification
Timers
Preliminary document
Specifications in this document are tentative and subject to change.
1. Overview
Outline of Specifications (3 / 7)
Module/Function
16-bit timer pulse unit
(TPUa)
Description
(16 bits × 6 channels) × 2 units*
1
Maximum of 32 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
(with maximum operating frequency of 75 MHz)
Input capture/output compare function
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Digital noise filtering of signals from the input capture pins
Event linking by the ELC
9 channels (16 bits × 8 channels, 32 bits × 1 channel)
Maximum of 28 pulse-input/output and 3 pulse-input possible
Select from among 9, 11, or 12 counter-input clock signals for each channel
(with maximum operating frequency of 150 MHz)
Input capture function
39 output compare/input capture registers
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffered operation
Support for cascade-connected operation
Automatic transfer of register data
Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired
duty cycles.
Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
Counter functionality for dead-time compensation
Generation of triggers for A/D converter conversion
A/D converter start triggers can be skipped
Digital noise filter function for signals on the input capture and external counter clock
pins
PPG output trigger can be generated
Event linking by the ELC
Multifunction timer pulse
unit (MTU3a)
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 4 of 52
Under development
RZ/T1 Group
Table 1.1
Classification
Timers
Preliminary document
Specifications in this document are tentative and subject to change.
1. Overview
Outline of Specifications (4 / 7)
Module/Function
General PWM timer
(GPTa)
Description
16 bits × 4 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Select from among four counter-input clock signals for each channel
(with maximum operating frequency of 150 MHz)
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: software, and compare-match
Generation of triggers for A/D converter conversion
Digital noise filter function for signals on the input capture and external trigger pins
Event linking by the ELC
(4 bits × 4 groups) × 2 units*
1
Pulse output with the MTU3a or TPUa output as a trigger
Maximum of 32 pulse-output possible
(16 bits × 2 channels) × 3 units
Select from among four counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Event linking by the ELC
(32 bits × 1 channel) × 2 units
Compare-match, input-capture input, and output-comparison output are available.
Select from among four counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
Interrupt requests can be output in response to compare-match, input-capture, and
output-comparison events.
Digital noise filter function for signals on the input capture pins
Event linking by the ELC
14 bits × 1 channel
Products incorporating an R-IN engine: 14 bits × 2 channels
Select from among six counter-input clock signals for each channel (with maximum
operating frequency of 75 MHz)
14 bits × 1 channel
Counter-input clock: Low-speed on-chip oscillator (LOCO)/2
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256 (with maximum operating frequency of 120
MHz)
Control of the high-impedance state of the MTU3a / GPTa's waveform output pins
4 pins for input from signal sources: POE0, POE4, POE8, POE10
Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
Initiation by input clock oscillation-stoppage detection, PLL oscillation anomaly
detection, or software
Additional programming of output control target pins is enabled
Programmable pulse
generator (PPG)
Compare match timer
(CMT)
Compare match timer W
(CMTW)
Watchdog timer (WDTA)
Independent watchdog
timer (IWDTa)
Port output enable 3
(POE3)
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 5 of 52
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