a
FEATURES
Low Offset Voltage: 50 V max
Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/√Hz max
High Gain (h
FE
):
500 min at I
C
= 1 mA
300 min at I
C
= 1 A
Excellent Log Conformance: r
BE
0.3
Low Offset Voltage Drift: 0.1 V/ C max
Improved Direct Replacement for LM194/394
Low Noise, Matched
Dual Monolithic Transistor
MAT02
PIN CONNECTION
TO-78
(H Suffix)
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
O
B
Input protection diodes are provided across the emitter-base
junctions to prevent degradation of the device characteristics
due to reverse-biased emitter current. The substrate is clamped
to the most negative emitter by the parasitic isolation junction
created by the protection diodes. This results in complete isola-
tion between the transistors.
SO
The design of the MAT02 series of NPN dual monolithic tran-
sistors is optimized for very low noise, low drift and low r
BE
.
Precision Monolithics’ exclusive Silicon Nitride “Triple-
Passivation” process stabilizes the critical device parameters
over wide ranges of temperature and elapsed time. Also, the high
current gain (h
FE
) of the MAT02 is maintained over a wide
range of collector current. Exceptional characteristics of the
MAT02 include offset voltage of 50
µV
max (A/E grades) and
150
µV
max F grade. Device performance is specified over the
full military temperature range as well as at 25°C.
LE
PRODUCT DESCRIPTION
The MAT02 should be used in any application where low
noise is a priority. The MAT02 can be used as an input
stage to make an amplifier with noise voltage of less than
1.0 nV/√Hz at 100 Hz. Other applications, such as log/antilog
circuits, may use the excellent logging conformity of the
MAT02. Typical bulk resistance is only 0.3
Ω
to 0.4
Ω.
The
MAT02 electrical characteristics approach those of an ideal
transistor when operated over a collector current range of 1
µA
to 10 mA. For applications requiring multiple devices
see MAT04 Quad Matched Transistor data sheet.
TE
NOTE
Substrate is connected to case on TO-78 package.
Substrate is normally connected to the most negative
circuit potential, but can be floated.
MAT02–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V
Parameter
Current Gain
Symbol
h
FE
CB
= 15 V, I
C
= 10 A, T
A
= 25 C, unless otherwise noted.)
MAT02E
Min Typ Max
500
500
400
300
605
590
550
485
0.5
10
10
10
5
5
30
0.3
25
35
35
MAT02F
Min Typ
Max
400
400
300
200
2
50
25
25
25
25
70
0.5
605
590
550
485
0.5
80
10
10
5
5
30
0.3
25
35
Unit
Conditions
I
C
= 1 mA
1
I
C
= 100
µA
I
C
= 10
µA
I
C
= 1
µA
10
µA ≤
I
C
≤
1 mA
2
V
CB
= 0, 1
µA ≤
I
C
≤
1 mA
3
0
≤
V
CB
≤
V
MAX4
1
µA ≤
I
C
≤
1 mA
3
V
CB
= 0 V
1
µA ≤
I
C
≤
1 mA
3
0
≤
V
CB
≤
V
MAX
10
µA ≤
I
C
≤
10 mA
5
V
CB
= V
MAX
V
CC
= V
MAX5, 6
V
CE
= V
MAX5, 6
V
BE
= 0
I
C
= 1 mA, V
CB
= 0
7
f
O
= 10 Hz
f
O
= 100 Hz
f
O
= 1 kHz
f
O
= 10 kHz
LE
1.6
0.9
0.85
0.85
2
1
1
1
0.05
0.1
25
0.6
40
200
23
35
40
–2–
Current Gain Match
Offset Voltage
Offset Voltage
Change vs. V
CB
Offset Voltage Change
vs. Collector Current
Offset Current
Change vs. V
CB
Bulk Resistance
Collector-Base
Leakage Current
Collector-Collector
Leakage Current
Collector-Emitter
Leakage Current
Noise Voltage Density
∆h
FE
V
OS
∆V
OS
/∆V
CB
∆V
OS
/∆I
C
∆I
OS
/∆V
CB
r
BE
I
CBO
I
CC
I
CES
e
n
4
150
50
50
50
50
70
0.5
400
400
%
µV
µV
µV
µV
µV
pA/V
Ω
pA
pA
pA
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
V
nA
nA
V
MHz
pF
pF
SO
I
C
= 10 mA, V
CE
= 10 V
V
CB
= 15 V, I
E
= 0
V
CC
= 0
Collector Saturation
Voltage
Input Bias Current
Input Offset Current
Breakdown Voltage
Gain-Bandwidth Product
Output Capacitance
Collector-Collector
Capacitance
V
CE(SAT)
I
B
I
OS
BV
CEO
f
T
C
OB
C
CC
I
C
= 1 mA, I
B
= 100
µA
I
C
= 10
µA
I
C
= 10
µA
Specifications subject to change without notice.
O
NOTES
1
Current gain is guaranteed with Collector-Base Voltage (V
CB
) swept from 0 to V
MAX
at the indicated collector currents.
2
Current gain match (∆h
FE
) is defined as:
∆h
FE =
100 (∆I
B
) (h
FE
min)
I
C
3
Measured at I
C
= 10
µA
and guaranteed by design over the specified range of I
C
.
4
This is the maximum change in V
OS
as V
CB
is swept from 0 V to 40 V.
5
Guaranteed by design.
6
I
CC
and I
CES
are verified by measurement of I
CBO
.
7
Sample tested.
B
TE
200
200
200
35
1.6
0.9
0.85
0.85
0.05
3
2
2
2
200
23
35
400
0.2
34
1.3
REV. E
MAT02
ELECTRICAL CHARACTERISTICS
(V
Parameter
Symbol
Conditions
CB
= 15 V, –25 C
≤
T
A
≤
+85 C, unless otherwise noted.)
MAT02E
Min Typ Max
MAT02F
Min Typ Max
Unit
Offset Voltage
Average Offset
Voltage Drift
Input Offset Current
Input Offset
Current Drift
Input Bias Current
Current Gain
V
OS
TCV
OS
I
OS
TCI
OS
I
B
h
FE
V
CB
= 0
1
µA ≤
I
C
≤
1 mA
1
10
µA ≤
I
C
≤
1 mA, 0
≤
V
CB
≤
V
MAX2
V
OS
Trimmed to Zero
3
I
C
= 10
µA
I
C
= 10
µA
4
I
C
= 10
µA
I
C
= 1 mA
5
I
C
= 100
µA
I
C
= 10
µA
I
C
= 1
µA
V
CB
= V
MAX
V
CE
= V
MAX
, V
BE
= 0
V
CC
= V
MAX
70
220
µV
µV/°C
nA
pA/°C
nA
0.08 0.3
0.03 0.1
8
40
325
275
225
200
90
45
300
250
200
150
0.08 1
0.03 0.3
13
40
150
50
NOTES
1
Measured at I
C
= 10
µA
and guaranteed by design over the specified range of I
C
.
2
3
Guaranteed by V
OS
test
(TCV
OS
≅
V
OS
T
for
V
OS
V
BE
) T = 298K
for T
A
= 25°C.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
O
Collector-Base Voltage (BV
CBO
) . . . . . . . . . . . . . . . . . . . . 40 V
Collector-Emitter Voltage (BV
CEO
) . . . . . . . . . . . . . . . . . . 40 V
Collector-Collector Voltage (BV
CC
) . . . . . . . . . . . . . . . . . . 40 V
Emitter-Emitter Voltage (BV
EE
) . . . . . . . . . . . . . . . . . . . . 40 V
Collector Current (I
C
) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Emitter Current (I
E
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Total Power Dissipation
Case Temperature
≤
40°C
2
. . . . . . . . . . . . . . . . . . . . . 1.8 W
Ambient Temperature
≤
70°C
3
. . . . . . . . . . . . . . . . 500 mW
Operating Temperature Range
MAT02E, F . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
B
SO
Model
MAT02EH
MAT02FH
V
OS
max
(T
A
= 25 C)
50
µV
150
µV
The initial zero offset voltage is established by adjusting the ratio of I
C
1 to I
C
2 at T
A
= 25°C. This ratio must be held to 0.003% over the entire temperature range.
Measurements are taken at the temperature extremes and 25°C.
4
Guaranteed by design.
5
Current gain is guaranteed with Collector-Base Voltage (V
CB
) swept from 0 V to V
MAX
at the indicated collector current.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT02 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
LE
ORDERING GUIDE
Collector-Base
Leakage Current
Collector-Emitter
Leakage Current
Collector-Collector
Leakage Current
I
CBO
I
CES
I
CC
TE
2
3
3
Temperature
Range
–25°C to +85°C
–25°C to +85°C
Package
Option
TO-78
TO-78
–3–
3
4
nA
nA
nA
4
Operating Junction Temperature . . . . . . . . . . –55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Junction Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
NOTES
1
Absolute maximum ratings apply to both DICE and packaged devices.
2
Rating applies to applications using heat sinking to control case temperature.
Derate linearly at 16.4 mW/°C for case temperature above 40°C.
3
Rating applies to applications not using a heat sinking; devices in free air only.
Derate linearly at 6.3 mW/°C for ambient temperature above 70°C.
WARNING!
ESD SENSITIVE DEVICE
REV. E
MAT02 –Typical Performance Characteristics
SO
–4–
TPC 4. Base-Emitter-On
Voltage vs. Collector Current
TPC 5. Small Signal Input
Resistance vs. Collector Current
O
B
TPC 7. Saturation Voltage
vs. Collector Current
TPC 8. Noise Voltage
Density vs. Frequency
TPC 9. Noise Voltage Density
vs. Collector Current
LE
TPC 6. Small-Signal Output
Conductance vs. Collector Current
TE
TPC 1. Current Gain vs.
Collector Current
TPC 2. Current Gain
vs. Temperature
TPC 3. Gain Bandwidth
vs. Collector Current
REV. E
MAT02
SO
TPC 13. Collector-to-Collector
Leakage vs. Temperature
O
B
TPC 16. Collector-to-Collector
Capacitance vs. Reverse Bias
Voltage
TPC 17. Emitter-Base Capacitance
vs. Reverse Bias Voltage
REV. E
LE
TPC 14. Collector-to-Collector
Capacitance vs. Collector-to
Substrate Voltage
TPC 15. Collector-Base
Capacitance vs. Reverse Bias Voltage
–5–
TE
TPC 10. Noise Current
Density vs. Frequency
TPC 11. Total Noise vs.
Collective Current
TPC 12. Collector-to-Base
Leakage vs. Temperature
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