AN4417
Application note
SPC564Axx/SPC56ELxx devices
Exception handling and single/double bit error
Introduction
This document provides an overview of SPC564Axx/SPC56ELxx exception handling with
main focus on different kinds of exception that the application code may face during the
runtime like single and double bit errors in memories, MPU protection violation, AIPS
access protection violation and others.
It starts with the simple overview of Machine check interrupt highlighting important things
from application perspective. To get detailed view and to implement low level machine
check interrupt handler, it is necessary to use Z4 Core User Manual which describes all the
details about the Core exception and interrupts.
The following part describes the reason of the exception, how to find it and what possibilities
exist to remove the fault.
December 2013
DocID025623 Rev 2
1/22
www.st.com
Contents
AN4417
Contents
1
Z4 Core exception overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Machine check interrupt (IVOR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.1
Machine check registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Machine check handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Low level handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1
2.1.2
2.1.3
Start phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Final phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Modification of the MCSRR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
User handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
SPC564Axx/SPC56ELxx exception cases . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Flash 2b ECC error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
Cause of the exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Machine check exception status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash 2b ECC error detection by ECSM . . . . . . . . . . . . . . . . . . . . . . . . 13
ECSM_ESR.FNCE implementation note for SPC564A70 device only . 14
ECSM_ESR implementation for SPC56ELx device only . . . . . . . . . . . . 14
Flash 2b ECC error detection by Flash controller . . . . . . . . . . . . . . . . . 14
Flash_x.MCR.ERR implementation note for SPC564A80 device only . 15
User exception handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Error solving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Appendix A Comparison of microcontroller behavior during ECC error . . . . . 17
Appendix B Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
B.1
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22
DocID025623 Rev 2
AN4417
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Machine check interrupt causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Machine check register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Machine check causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPC564Axx/SPC56ELxx exception causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash 2b ECC - machine check exception status in core registers. . . . . . . . . . . . . . . . . . . 13
Flash 2b ECC – ECSM registers related to ECC error detection . . . . . . . . . . . . . . . . . . . . 13
Flash 2b ECC – flash controller registers related to ECC error detection. . . . . . . . . . . . . . 15
Summary of reactions to single/double bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID025623 Rev 2
3/22
3
List of figures
AN4417
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Machine check exception flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Modification of MCSRR0 register content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Machine check exception user handler flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash 2b ECC error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4/22
DocID025623 Rev 2
AN4417
Z4 Core exception overview
1
Z4 Core exception overview
Z4 Core used on SPC564Axx/SPC56ELxx devices contains many exception sources and
sixteen interrupts to service them. Multiple exception sources can be mapped to one
interrupt handler where few supportive status registers provide flags to find the cause of the
exception in the handler.
Detailed list of the exception causes and their mapping to interrupt handlers is found in the
Z4 Core Reference Manual (see
Section Appendix B: Reference documents).
This chapter gives an overview of machine check interrupt that is utilized for several
important fault states of SPC564Axx/SPC56ELxx devices.
1.1
Machine check interrupt (IVOR1)
Machine check interrupt is a handler that services multiple fault events that may occur
during runtime code execution.
Table 1. Machine check interrupt causes
Interrupt type
Exception conditions
-NMI
-ISI, ITLB, Error on first instruction fetch for an exception handler
-Parity Error signaled on cache access
-External bus error
Machine check
This interrupt is used to handle various faults generated by peripherals in the
SPC564Axx/SPC56ELxx devices, like MPU protection fault, 2b ECC error in the Flash or
RAM memory etc. The reason is that most of the faults are signaled back as external bus
error situation during the CPU-Submodule bus transaction.
1.1.1
Machine check registers
Z4 core implements few machine check status registers that are updated upon the
exception event with some constraints stated in the Z4 Core Reference Manual (see
Section Appendix B: Reference documents).
These registers are used to find the source of
the exception and based on, it is decided how to solve it.
DocID025623 Rev 2
5/22
21
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
