HD49235FS
Digital Signal Processor for CD
ADE-207-162A(Z)
2nd. Edition
August 1995
Description
The HD49235FS is a digital signal processor for compact disc (CD) applications.
Features
•
Powerful error correction capability: two-symbol C1 correction and four-symbol C2 correction
•
Quadruple-speed reproduction supported (maintaining two-symbol C1 and four-symbol C2 error
correction)
•
On-chip analog PLL and digital PLL (VCO and phase detector)
•
Automatic adjustment of the free-running frequency of the VCO
•
Built-in microprocessor interface
•
On-chip 80-bit shift registers for Q-code buffering
•
Cyclic redundancy check on Q-code values
•
Audio output functions: monaural output, single-channel mute, left-right reverse, soft mute, –12-dB
attenuation
•
16-kbit RAM on-chip
HD49235FS
Pin Arrangement
PDOUT1
V
DD
(A)
AMPP
AMPM
AMPO
AC
V
SS
(A)
PDOUT2
TEST1
MRST
PLLCK
NC
V
DD
(D)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
QDSEL
DSLCO
DSLCI
EFMI
DEFCT
TEST2
TEST3
UCKSL
V
DD
(D)
PWM
MON
MSTOP
PW64
ROTD
CLVS
SLOCK
64
65
41
40
80
1
25
24
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
(D)
XCI
XCO
NC
MCK
TC1
UCK
Rev.2, Aug. 1995, page 2 of 41
XRST
CNIN
SENS
DATA
CLK
XLT
V
SS
(D)
OVFW
S1
QOK
QDATA
CKEXT
SUBOUT
SUBCK
CFCKP
EMP
BIDAT
MUTE
DAS
CKX
MPX
C2F
QMX
DMX
(Top view)
HD49235FS
Pin Description
Pin
No. Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XRST
CNIN
SENS
DATA
CLK
XLT
V
SS
(D)
OVFW
S1
QOK
QDATA
CKEXT
Name
X (µ-com)
reset
Counter clock
input
Sensor
Data
Clock
I/O*
I
I
TO
I
I
Connection
Function
Polarity
H
L
Reset
Microprocessor Microprocessor interface
register reset
Servo IC
Pulse input for track counter
Microprocessor Servo status output
Microprocessor Data input for microprocessor
interface
Microprocessor Clock input for microprocessor
interface
Microprocessor Strobe input for
microprocessor interface
Digital ground
On-chip RAM overflow signal
output
Microprocessor Subcode sync signal
(with protection)
Microprocessor Subcode CRC result output
Microprocessor Subcode Q data output
Microprocessor Clock input for Q data readout
CD graphics
CD graphics
CD graphics
Subcode data output for CD
graphics
Clock input for SUBOUT
subcode readout
Subcode frame
synchronization signal (7.35
kHz at normal speed,
synchronized with PLL)
Emphasis on/off status output ON
Digital audio interface output
Microprocessor Audio mute input
DAC or ROM
decoder
DAC or ROM
decoder
Serial data output for audio or
ROM
Strobe clock output for DAS
signal
Mute
OFF
OK
NG
Overflow
X (µ-com) latch I
V
SS
(digital)
—
RAM- overflow O
Subcode sync O
1
Q-code OK
Q-code data
Clock-EXT
O
O
I
O
SUBOUT Subcode out
SUBCK
CFCKP
Subcode clock I
C&D frame
clock out
O
16
17
18
19
20
EMP
BIDAT
MUTE
DAS
CKX
Emphasis
output
Biphase date
Mute
O
TO
I
Data serial out O
Clock X
O
Rev.2, Aug. 1995, page 3 of 41
HD49235FS
Pin Description
(cont)
Pin
No. Symbol
21
MPX
Name
Multiplex
I/O*
O
Connection
DAC or ROM
decoder
Function
Left/right channel switching
signal output (44.1 kHz at
normal speed, synchronized
with DAS)
C2 error flag output
4
×
MPX clock signal
(176.4 kHz at normal speed,
synchronized with DAS)
2
×
MPX clock signal
(88.2 kHz at normal speed,
synchronized with DAS)
Microprocessor Clock output for
microprocessor
(8.5 MHz or 17 MHz)
C1 error flag monitor pin
Master clock output
(33.8688 MHz)
Open or VDD
Crystal
oscillator
Crystal
oscillator
Not connected
Crystal oscillator output
Crystal oscillator input
Digital ground
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Error
Error
Polarity
H
L
22
23
C2F
QMX
C2 flag
O
ROM decoder
Quad multiplex O
24
DMX
Double
multiplex
µ-com clock
O
25
UCK
O
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TC1
MCK
NC
XCO
XCI
V
SS
(D)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Test C1 flag
Master clock
O
O
No connection —
X’tal clock
output
X’tal clock
input
V
SS
(digital)
XO
XI
—
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
Rev.2, Aug. 1995, page 4 of 41
HD49235FS
Pin Description
(cont)
Pin
No. Symbol
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
NC
NC
NC
NC
NC
NC
NC
V
DD
(D)
NC
PLLCK
MRST
TEST1
Name
I/O*
Connection
Open
Open
Open
Open
Open
Open
Open
Function
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Digital power supply
Open or V
DD
Open or V
DD
Open or V
DD
External RC
circuit
Not connected
PLL clock output monitor
Master reset of chip
Test pin
PLL auto-adjust phase
detector output
Analog ground
External RC
circuit
External RC
circuit
External RC
circuit
External RC
circuit
Amplifier phase compensation
pin
PLL amplifier output
PLL amplifier inverting input
PLL amplifier non-inverting
input
Analog power supply
External RC
circuit
PLL EFM phase detector
output
Q data readout mode
switching signal input
External RC
circuit
External RC
circuit
EFM comparator slice level
control output
EFM comparator slice level
control input
EFM signal input
Servo IC
Open or V
DD
Defect detection signal input
Test pin
Defect
Internal
sync
External
sync
Reset
Polarity
H
L
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
No connection —
V
DD
(digital)
PLL clock
Master reset
TEST 1
—
No connection —
O
IU
IU
TO
—
A
AO
AI
PDOUT2 Phase detect
out 2
V
SS
(A)
AC
AMPO
AMPM
AMPP
V
DD
(A)
V
SS
(analog)
Amp
compensation
Amp output
Amp minus
input
Amp plus input AI
V
DD
(analog)
—
TO
IU
O
AI
AI
I
IU
PDOUT1 Phase detect
out 1
QDSEL
DSLCO
DSLCI
EFMI
DEFCT
TEST2
Q-data clock
select
DSL control
output
DSL control
input
EFM signal
input
Defect
TEST 2
Rev.2, Aug. 1995, page 5 of 41
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