AN3065
Application note
100 W transition-mode PFC pre-regulator with the L6563S
Introduction
This application note describes a demonstration board based on the transition-mode PFC
controller L6563S and presents the results of its bench demonstration. The board
implements a 100 W, wide-range mains input, PFC pre-conditioner suitable for ballast,
adapters, flatscreen displays, and all SMPS having to meet the IEC61000-3-2 or the JEITA-
MITI regulation.
The L6563S is a current-mode PFC controller operating in transition mode (TM) and
implementing an internal high-voltage startup circuitry.
Figure 1.
EVL6563S-100W: L6563S 100W TM PFC demonstration board
September 2010
Doc ID 16279 Rev 2
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Contents
AN3065
Contents
1
2
3
4
Main characteristics and circuit description . . . . . . . . . . . . . . . . . . . . . 4
Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test results and significant waveforms . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Harmonic content measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Inductor current in TM and L6563S THD optimizer . . . . . . . . . . . . . . . . . 12
Voltage feed-forward and brownout function . . . . . . . . . . . . . . . . . . . . . . 15
Startup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PFC_OK pin and feedback failure (open loop) protection . . . . . . . . . . . . 20
TBO (tracking boost option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power management and housekeeping functions . . . . . . . . . . . . . . . . . . 23
5
6
7
Layout hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
EMI filtering and conducted EMI pre-compliance measurements . . . 27
PFC coil specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
7.3
7.4
7.5
7.6
General description and characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Winding characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Unit identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
9
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Doc ID 16279 Rev 2
AN3065
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
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Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
EVL6563S-100W: L6563S 100W TM PFC demonstration board . . . . . . . . . . . . . . . . . . . . . 1
EVL6563S-100W TM PFC demonstration board: electrical schematic . . . . . . . . . . . . . . . . 6
EVL6563S-100W TM PFC: compliance to EN61000-3-2 standard . . . . . . . . . . . . . . . . . . 10
EVL6563S-100W TM PFC: compliance to JEITA-MITI standard . . . . . . . . . . . . . . . . . . . . 10
EVL6563S-100W TM PFC: input current waveform at 230 V, 50 Hz, 100 W load . . . . . . . 11
EVL6563S-100W TM PFC: input current waveform at 100 V, 50 Hz, 100 W load . . . . . . . 11
EVL6563S-100W TM PFC: power factor vs. output power. . . . . . . . . . . . . . . . . . . . . . . . . 11
EVL6563S-100W TM PFC: THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EVL6563S-100W TM PFC: efficiency vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EVL6563S-100W TM PFC: average efficiency acc. to ES-2 . . . . . . . . . . . . . . . . . . . . . . . 12
EVL6563S-100W TM PFC: static Vout regulation vs. output power. . . . . . . . . . . . . . . . . . 12
EVL6563H 100W TM PFC: Vds and inductor current at 100 Vac, 50 Hz, full load. . . . . . . 13
EVL6563H 100W TM PFC: Vds and inductor current at 100 Vac, 50 Hz, full load (detail). 13
EVL6563H 100W TM PFC: Vds and inductor current at 230 Vac, 50 Hz, full load. . . . . . . 14
EVL6563H 100W TM PFC: Vds and inductor current at 230 Vac, 50 Hz, full load (detail). 14
EVL6563S-100W TM PFC: Vds and inductor current at 100 Vac, 50 Hz, full load. . . . . . . 15
EVL6563S-100W TM PFC: Vds and inductor current at 230 Vac, 50 Hz, full load. . . . . . . 15
L6562A input mains surge 90 Vac to 140 Vac, no VFF input . . . . . . . . . . . . . . . . . . . . . . . 16
EVL6563S-100W TM PFC: input mains surge 90 Vac to 140 Vac . . . . . . . . . . . . . . . . . . . 16
L6562A input mains dip 140 Vac to 90 Vac, no VFF input . . . . . . . . . . . . . . . . . . . . . . . . . 17
EVL6563S-100W TM PFC: input mains dip 140 Vac to 90 Vac . . . . . . . . . . . . . . . . . . . . . 17
L6563: input current at 100 Vac, 50 Hz, CFF=0.47 µF, RFF=390 kΩ. . . . . . . . . . . . . . . . . 18
EVL6563S-100W TM PFC: input current at 100 Vac, 50 Hz, CFF=1 µF, RFF=1 MΩ . . . . 18
EVL6563S-100W TM PFC startup attempt at 80Vac, 60 Hz, full load . . . . . . . . . . . . . . . . 19
EVL6563S-100W TM PFC: startup with slow input voltage increasing, full load . . . . . . . . 19
EVL6533S-100W TM PFC: turn-off with slow input voltage decreasing, full load . . . . . . . 19
EVL6563S-100W TM PFC startup at 90 Vac, 60 Hz, full load . . . . . . . . . . . . . . . . . . . . . . 20
EVL6563S-100W TM PFC startup at 265 Vac, 50 Hz, full load . . . . . . . . . . . . . . . . . . . . . 20
EVL6563S-100W TM PFC load transient at 115 Vac, 60 Hz, full load to no load . . . . . . . 22
EVL6563S-100W TM PFC open loop at 115 Vac, 60 Hz, full load . . . . . . . . . . . . . . . . . . . 22
L6563S on/off control by a cascaded converter controller via the PFC_OK or RUN pin . . 23
Interface circuits that let the L6563S switch on or off a PWM controller, not latched . . . . . 24
Interface circuits that let the L6563S switch on or off a PWM controller, latched . . . . . . . . 24
EVL6563S-100W TM PFC PCB layout (SMT side view) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EVL6563S-100W TM PFC CE peak measurement at 100 Vac, 50 Hz, full load, phase . . 27
EVL6563S-100W TM PFC CE peak measurement at 100 Vac, 50 Hz, full load, neutral . . 27
EVL6563S-100W TM PFC CE peak measurement at 230 Vac, 50 Hz, full load, phase . . 28
EVL6563S-100W TM PFC CE peak measurement at 230 Vac, 50 Hz, full load, neutral . . 28
Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Main characteristics and circuit description
AN3065
1
Main characteristics and circuit description
The main characteristics of the SMPS are listed below:
●
●
●
●
●
●
●
●
●
●
Line voltage range: 90 to 265 Vac
Minimum line frequency (f
L
): 47 Hz
Regulated output voltage: 400 V
Rated output power: 100 W
Maximum 2f
L
output voltage ripple: 20 V pk-pk
Hold-up time: 10 ms (V
DROP
after hold-up time: 300 V)
Minimum switching frequency: 40 kHz
Minimum estimated efficiency: 92% (at Vin = 90 Vac, Pout = 100 W)
Maximum ambient temperature: 50 °C
PCB type and size: single side, 35 µm, CEM-1, 90 x 83 mm
This demonstration board implements a power factor correction (PFC) pre-regulator,100 W
continuous power, on a regulated 400 V rail from a wide-range mains voltage and provides
for the reduction of the mains harmonics, allowing to meet the European EN61000-3-2 or
the Japanese JEITA-MITI standard. The regulated output voltage is typically the input for the
cascaded isolated DC-DC converter that provides the output rails required by the load.
The board is designed to allow full-load operation in still air.
The power stage of the PFC is a conventional boost converter, connected to the output of
the rectifier bridge D1. It is completed by the coil L2, the diode D3 and the capacitor C6. The
boost switch is represented by the power MOSFET Q1. The NTC R1 limits the inrush
current at switch-on. It has been connected on the DC rail, in series to the output electrolytic
capacitor, in order to improve the efficiency during low line operation because the RMS
current flowing into the output stage is lower than current flowing into the input one at the
same input voltage, thus increasing efficiency. The board is equipped with an input EMI filter
necessary to filter the commutation noise coming from the boost stage.
At startup the L6563S is powered by the capacitor C11 that is charged via the resistors R7
and R16. Then the L2 secondary winding and the charge pump circuit (C7, R4, D4 and D5)
generate the Vcc voltage powering the L6563S during normal operation. The L2 secondary
winding is also connected to the L6563S pin #11 (ZCD) through the resistor R5. Its purpose
is supply the information that L2 has demagnetized, needed by the internal logic for
triggering a new switching cycle.
The divider R9, R12, R17 and R19 provides the L6563S multiplier with the information of the
instantaneous mains voltage that is used to modulate the peak current of the boost.
The resistors R2, R8, R10 with R13 and R14 are dedicated to sense the output voltage and
feed back to the L6563S the information necessary to regulate the output voltage. The
components C9, R18 and C8 constitute the error amplifier compensation network necessary
to keep the required loop stability.
The peak current is sensed by resistors R25 and R26 in series to the MOSFET and signal is
fed into pin #4 (CS) of the L6563S via the filter composed of R24 and C15.
C13, R27 and R32 connected to pin #5 (V
FF
) complete an internal peak-holding circuit that
derives the information on the RMS mains voltage. The voltage signal at this pin, a DC level
equal to the peak voltage on pin #3 (MULT), is fed to a second input to the multiplier for the
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Doc ID 16279 Rev 2
AN3065
Main characteristics and circuit description
1/V
2
function necessary to compensate the control loop gain dependence on the mains
voltage. Additionally, pin #10 (RUN) is connected to pin# 5 (V
FF
) through a resistor divider
R27 and R32, providing a voltage threshold for brownout protection (AC mains
undervoltage). A voltage below 0.8 V shuts down (not latched) the IC and brings its
consumption to a considerably lower level. The L6563S restarts as the voltage at the pin
rises above 0.88 V.
The divider R3, R6, R11 and R15 provides the L6563S pin #7 (PFC_OK) with the
information regarding the output voltage level. It is required by the L6563S output voltage
monitoring and disables functions used for PFC protection purposes.
If the voltage on pin #7 exceeds 2.5 V, the IC stops switching and restarts as the voltage on
the pin falls below 2.4 V implementing the so-called dynamic OVP, which prevents an
excessive output voltage in case of transients, because of the slow response of the error
amplifier. However, if contemporaneously the voltage of the INV pin falls below 1.66 V (typ.),
a feedback failure is assumed. In this case the device is latched off. Normal operation can
be resumed only by cycling Vcc, bringing its value lower than 6 V before rising up to the
turn-on threshold.
Additionally If the voltage on pin #7 (PFC_OK) is tied below 0.23 V, the L6563S is shut
down. To restart operation of the L6563S the voltage on pin #7 (PFC_OK) has to increase
above 0.27 V. This function can be used as a remote on/off control input.
To allow interfacing of the board with a D2D converter, the connector J3 allows powering the
L6563S with an external Vcc and also manages failure or abnormal conditions via the pins
PWM_LATCH and PWM_STOP. The L6563S can be also disabled or enabled to manage
properly light load or failure by the D2D via the PFC_OK pin (#7), available at pin #5 of J3
(ON/OFF). For further details please see
Section 4.7.
Doc ID 16279 Rev 2
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