The HV100/HV101 are 3-pin hotswap controllers available in
SOT-223 and MLP packages, which require no external compo-
nents other than a pass element. The HV100/HV101 contain
many of the features found in hotswap controllers with 8 pins or
more, and which generally require many external components.
These features include undervoltage (UV) detection circuits,
power on reset (POR) supervisory circuits, inrush current limit-
ing, short circuit protection, and auto-retry. In addition, the
HV100/HV101 use a patent pending mechanism to sample and
adapt to any pass element, resulting in consistent hotswap
profiles without any programming.
The only difference between the HV100 and the HV101 is the
internally set undervoltage (UV) threshold.
Features
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
33% Smaller than SOT-23
2
Pass Element is Only External Part
No Sense Resistor required
Auto-Adapt* to Pass Element
Short Circuit Protection*
UV & POR Supervisory Circuits
2.5s Auto Retry
±10V
to
±72V
Input Voltage Range
0.6mA Typical Operating Supply Current
Built in Clamp for AC Path Turn On Glitch
Applications
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
-48V Central Office Switching (line cards)
+48V Server Networks
+48V Storage Area Networks
+48V Peripherals, Routers, Switches
+24V Cellular and Fixed Wireless (bay stations, line cards)
+24V Industrial Systems
+24V UPS Systems
-48V PBX & ADSL Systems (line cards)
Distributed Power Systems
Powered Ethernet for VoIP
Ordering Information
UV
Options
34V
14V
Package Options
3-Pin SOT-223 3-Pin MLP
HV100K5
HV100K6
HV101K5
HV101K6
Die
HV100X
HV101X
Typical Applications and Waveforms
GND
V
PP
400µF
DC/DC
Converter
+5V
COM
HV100
GATE
V
NN
-48V
IRF530
*Patents Pending
1
IRF530 is a Trademark of International Rectifier Corporation
2
MLP3x2 Package Version compared to 3mmx3mm SOT-23-6
05/21/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
HV100/HV101
Electrical Characteristics
(-40°C < T
A
< +85°C unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Supply
(Referenced to V
PP
pin)
V
NN
I
NN
Supply Voltage
Supply Current
-72
0.6
UV
1.0
V
mA
V
NN
= -48V
UV Control
(Referenced to V
NN
pin)
V
UVL
V
UVH
UV Threshold (High to Low)
UV Hysteresis
30
12.3
34
14
3
1
38
15.7
V
V
V
V
HV100
HV101
HV100
HV101
Gate Drive Output
(Referenced to V
NN
pin)
V
GATE
SR
GATE
I
GATEDOWN
I
PULLUP
Maximum Gate Drive Voltage
Initial Slew Rate
Gate Drive Pull-Down Current (sinking)
Post Hot Swap Pull-up Current
10
1.75
8
6
12
2.5
16
11
14
3.25
V
V/ms
mA
µA
C
GATE
= 1nF
V
GATE
= 1V; V
PP
= 11.5V
V
GATE
= 6V
Timing Control
(Referenced to V
NN
pin)
t
POR
t
ARD
Insertion POR Delay
Auto Restart Delay
1.5
1.25
3.5
2.5
5.5
3.75
ms
s
Example Electrical Results
(Using IRF530)
I
LIM
I
LIM
I
LIM
I
SHORT
t
SHORT
∆
GATE
t
HS
Max Inrush Current During Hotswap
Max Inrush Current During Hotswap
Max Inrush Current During Hotswap
Max Current Into a Short
Shorted Load Detec Time
Initial Rate of Rise of Gate
Hot Swap Period to Full Gate Voltage
1.4
2.5
3.1
4.0
1.0
2.5
12.5
A
A
A
A
ms
V/ms
ms
IRF530 external MOSFET, C
LOAD
= 100µF
IRF530 external MOSFET, C
LOAD
= 200µF
IRF530 external MOSFET, C
LOAD
= 300µF
IRF530 external MOSFET, R
LOAD
= <<1
IRF530 external MOSFET, R
LOAD
= <<1
IRF530 external MOSFET, any C
LOAD
IRF530 external MOSFET, any C
LOAD
Absolute Maximum Ratings*
V
PP
Input Voltage
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
*All voltages referenced to V
NN
.
Pinouts
2
-0.3V to 75V
-40°C to +85°C
-40°C to 125°C
-65°C to 150°C
Top View
SOT-223
1
VPP
2
VNN
3
GATE
Pin Description
V
PP
V
NN
GATE
– Positive voltage supply input to the circuit.
– This pin is the Negative voltage power supply input to
the circuit.
– This is the Gate Driver Output for the external N-
Channel MOSFET.
VNN
2
Top View
3 pin MLP
1
VPP
3
GATE
2
HV100/HV101
Functional Block Diagram
VPP
Regulator
UVLO
Reference
Generator
UV
POR
Timer
Logic
Restart
Timer
GATE
VNN
Functional Description
Insertion into Hot Backplanes
Telecom, data network and some computer applications require
the ability to insert and remove circuit cards from systems
without powering down the entire system. Since all circuit cards
have some filter capacitance on the power rails, which is espe-
cially true in circuit cards or network terminal equipment utilizing
distributed power systems, the insertion can result in high inrush
currents that can cause damage to connector and circuit cards
and may result in unacceptable disturbances on the system
backplane power rails.
The HV100/HV101 are designed to facilitate the insertion and
removal of these circuit cards or connection of terminal equip-
ment by eliminating these inrush currents and powering up these
circuits in a controlled manner after full connector insertion has
been achieved. The HV100/HV101 are intended to provide this
control function on the negative supply rail.
After completion of a full POR period, the MOSFET gate Auto-
Adapt operation begins. A reference current source is turned on
which begins to charge an internal capacitor generating a ramp
voltage which rises at a slew rate of 2.5 V/ms. This reference
slew rate is used by a closed loop system to generate a GATE
output current to drive the gate of the external N-channel
MOSFET with a slew rate that matches the reference slew rate.
Before the gate crosses a reference voltage, which is well below
the V
TH
of industry standard MOSFETs, the pull-up current value
is stored and the Auto-Adapt loop is opened. This stored pull-up
current value is used to drive the gate during the remainder of the
hot swap period. The result is a normalization with C
ISS
, which
for most MOSFETs scales with C
RSS
.
The MOSFET gate is charged with a current source until it
reaches its turn on threshold and starts to charge the load
capacitor. At this point the onset of the Miller Effect causes the
effective capacitance looking into the gate to rise, and the current
source charging the gate will have little effect on the gate voltage.
The gate voltage remains essentially constant until the output
capacitor is fully charged. At this point the voltage on the gate of
the MOSFET continues to rise to a voltage level that guarantees
full turn on of the MOSFET. It will remain in the full on state until
an input under voltage condition is detected.
If the circuit attempts turn on into a shorted load, then the Miller
Effect will not occur. The gate voltage will continue to rise
essentially at the same rate as the reference ramp indicating that
a short circuit exists. This is detected by the control circuit and
results in turning off the MOSFET initiating a 2.5 second delay,
after which a normal restart is attempted.
If at any time during the start up cycle or thereafter, the input
voltage falls below the UV threshold the GATE output will be
pulled down to V
NN
, turning off the N-channel MOSFET and all
internal circuitry is reset. A normal restart sequence will be
initiated once the input voltage rises above the UVLO threshold
plus hysteresis.
Description of Operation
On initial power application the high input voltage internal regu-
lator seeks to provide a regulated supply for the internal circuitry.
Until the proper internal voltage is achieved all circuits are held
reset by the internal UVLO and the gate to source voltage of the
external N-channel MOSFET is held off. Once the internal
regulator voltage exceeds the UVLO threshold, the input
undervoltage detection circuit (UV) senses the input voltage to
confirm that it is above the internally programmed threshold. If
at any time the input voltage falls below the UV threshold, all
internal circuitry is reset and the GATE output is pulled down to
V
NN
. UVLO detection works in conjunction with a power on reset
(POR) timer of approximately 3.5ms to overcome contact bounce.
Once the UVLO is satisfied the gate is held to V
NN
until a POR
timer expires. Should the UV monitor toggle before the POR
timer expires, the POR timer will be reset. This process will be
repeated each time UVLO is satisfied until a full POR period has
been achieved.
3
HV100/HV101
Application Information
Turn On Clamp
Hotswap controllers using a MOSFET as the pass element all
include a capacitor divider from V
PP
to V
NN
through C
LOAD
, C
RSS
and C
GS
. In most competitive solutions a large external capacitor
is added to the gate of the pass element to limit the voltage on
the gate resulting from this divider. In those instances if a gate
capacitor is not used the internal circuitry is not available to hold
off the gate and therefore a fast rising voltage input will cause the
pass element to turn on for a moment. This allows current spikes
to pass through the MOSFET.
The HV100/HV101 include a built-in clamp to ensure that this
spurious current glitch does not occur. The built-in clamp will
work for the time constants of most mechanical connectors.
There may be applications, however, that have rise times that
are much less than 1µs (100’s of ns). In these instances it may
be necessary to add a capacitor from the MOSFET gate to
source to clamp the gate and suppress this current spike. In
these cases the current spike generally contains very little
energy and does not cause damage even if a capacitor is not
used at the gate.
Short Circuit Protection
The HV100/HV101 provide short circuit protection by shutting
down if the Miller Effect associated with hotswap does not occur.
Specifically, if the output is shorted then the gate will rise without
exhibiting a “flat response”. Due to the fact that we have normal-
ized the hotswap period for any pass element, a timer can be
used to detect if the gate voltage rises above a threshold within
that time, indicating that a short exists. The diagram below
shows a typical turn on sequence with the load shorted, resulting
in a peak current of 4A.
2A/div
Auto-Adapt Operation
The HV100/HV101 Auto-adapt mechanism provides an impor-
tant function. It normalizes the hotswap period regardless of
pass element or load capacitor for consistent hotswap results.
By doing this it allows the novel short circuit mechanism to work
because the mechanism requires a known time base.
The maximum current that may occur during this period can be
controlled by adding a resistor in series with the source of the
MOSFET. The lower graph shows the same circuit with a 100mΩ
resistor inserted between source and V
NN
. In this case the
maximum current is 25% smaller.
The above diagram illustrates the effectiveness of the auto-
adapt mechanism. In this example three MOSFETs with different
C
ISS
and R
DSON
values are used. The top waveform is the hotswap
current, while the bottom waveform is the gate voltage. As can
be seen, the hotswap period is normalized, the initial slope of the
gate voltage is approximately 2.5V/ms regardless of the MOSFET,
and the total hotswap period and peak currents are a function of
a MOSFET type dependent constant multiplied by C
LOAD
.
Typically if MOSFETs of the same type are used, the hotswap
results will be extremely consistent. If different types are used
they will usually exhibit minimal variation.
For most applications and pass elements, the HV100/HV101
provides adequate limiting of the maximum current to prevent
damage without the need for any external components. The 2.5s
delay of the auto-retry circuit provides time for the pass element
to cool between attempts.
NTE66 is a trademark of NTE Electronics
IRF530 is a trademark of International Rectifier Corporation
IRF120M is a trademark of International Rectifier Corporation
4
HV100/HV101
Application Information, cont’d.
Auto-Retry
Not only does the HV100/HV101 provide short circuit protection
in a 3-pin package, it also includes a 2.5s built in auto-restart
timer. The HV100/HV101 will continuously try to turn on the
system every 2.5s, providing sufficient time for the pass element
to cool down after each attempt.
Programming the HV100/HV101
The HV100/HV101 require no external components other than a
pass element to provide the functionality described thus far. In
some applications it may be useful to use external components
to adjust the maximum allowable inrush current, adjust UVLO, or
to provide additional gate clamping if the supply rails have rise
times below 1ms.
All of the above are possible with a minimum number of external
components.
i)
To adjust inrush current with an external component simply
connect a capacitor (C
FB
) from drain to gate of the MOSFET.
The inrush calculation then becomes:
I
INRUSH
=
2A/div
(
C
FB
+
C
ISS
)
* 2.5E3 * C
LOAD
(
C
RSS
+
C
FB
)
Note that a resistor (approximately 10KΩ) needs to be
added in series with C
FB
to create a zero in the feedback loop
and limit the spurious turn on which is now enhanced by the
larger divider element.
ii)
Calculating Inrush Current
As can be seen in the diagram below, for a standard pass
element, the HV100/HV101 will normalize the hotswap time
period against load capacitance. For this reason the current limit
will increase with increasing value of the load capacitance.
To increase undervoltage lockout simply connect a Zener
diode in series with the V
PP
pin.
iii) If the V
PP
rises particularly fast (>48e6V/s) then it may be
desirable to connect a capacitor from gate to source of the
MOSFET to provide a path for the power application tran-
sient spike, which is now too fast for the internal clamping
mechanism.
iv) To limit the peak current during a short circuit, a resistor in
series with the source of the MOSFET may help.
Implementing PWRGD Control
Due to the HV100/HV101’s small footprint, it is possible to create
an open drain PWRGD signal using external components and
still maintain a size comparable with the smallest hotswap
controllers available elsewhere. To accomplish this an external
MOSFET may be used in conjunction with the gate output.
Simply use a high impedance divider (10MΩ) sized so that the
open drain PWRGD MOSFET threshold will only be reached
once the HV100/HV101’s gate voltage rises well above the
current limit value required by the external MOSFET pass
device. Alternatively a Zener diode between the gate output and
the PWRGD MOSFET gate set at a voltage higher than the
maximum pass element Vt will also work.
Inrush can be calculated from the following formula:
I
INRUSH(PEAK)
= (C
ISS
/ C
RSS
) * 2.5e3 * C
LOAD
This is a surprisingly consistent result because for most MOSFETs
of a particular type the ratio of C
ISS
/ C
RSS
is relatively constant
(though notice from the plot that there is some variation) even
while the absolute value of these and other quantities vary.
Based on this, the inrush current will vary primarily with C
LOAD
.
This makes designing with the HV100/HV101 particularly easy
because once the pass element is chosen, the period is fixed and
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
