LTC1428-50
Micropower 8-Bit Current
Sink Output D/A Converter
FEATURES
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DESCRIPTION
The LTC
®
1428-50 is a micropower 8-bit current sink
output D/A converter (DAC) with an output range of 0µA to
50µA. In 3.3V or 5V systems, the DAC I
OUT
pin can be
biased from 2V to 10V. Supply current is only 130µA.
Shutdown mode drops the supply current to 0.2µA.
The LTC1428-50 communicates with external circuitry by
using one of three interface modes: standard 3-wire serial
mode or one of two pulse modes. Upon power-up, the
internal counter resets to 10000000B, the DAC output
assumes midrange and the chip configures to 3-wire or
pulse mode depending on the CS signal level.
In 3-wire mode, the system MPU can serially transfer
8-bit data to and from the LTC1428-50. In pulse mode, the
upper six bits of the DAC output program for increment-
only (1-wire interface) or increment/decrement (2-wire
interface) operation depending on the D
IN
signal level. In
increment-only mode, the counter rolls over and sets the
DAC to zero if the counter increases beyond full scale. In
increment/decrement mode, the counter stops
incrementing at full scale, stops decrementing at zero
scale and does not roll over.
LTC1428-50 is available in an 8-pin SO package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Triple Mode is a trademark of Linear Technology Corporation.
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Precision Full-Scale DAC Output Current
at 25°C: 50µA
±3%
Wide Output Voltage DC Compliance: 2V to 10V
Wide Supply Range: 3V
≤
V
CC
≤
6.5V
Supply Current in Shutdown: 0.2µA
Low Supply Current: 130µA
Available in 8-Pin SO
Triple Mode
TM
Interface
1. Standard 3-Wire Mode
2. 1-Wire Pulse Mode Interface: Increment-Only
3. 2-Wire Pulse Mode Interface: Increment/Decrement
DAC Value Read Back Capability in 3-Wire Mode
DAC Powers Up at Midrange
DAC Contents Are Retained in Shutdown
APPLICATIONS
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LCD Contrast Control
Backlight Brightness Control
Power Supply Voltage Adjustment
Battery Charger Voltage/Current Adjustment
GaAs FET Bias Adjustment
Trimmer Pot Elimination
TYPICAL APPLICATION
Digitally Controlled LCD Bias Generator (Standard 3-Wire Mode)
L1
D1
V
OUT
15.75V TO 27.75V IN STEPS OF 47mV
15mA FROM 2 CELLS
5V
1
R2
22k
R3
22k
2
I
OUT
V
CC
D
OUT
D
IN
8
7
V
CC
MPU
(e.g., 8051)
P1.3
P1.2
P1.1
P1.0
1428-50 TA01
R1
240k
SHDN
2
CELLS
1µF
V
IN
SHDN
SW
LT
®
1307
FB
GND
V
C
4700pF
100k
L1: 4.7µH MURATA-ERIE LQH3C
D1: MBR0530 OR 1N4148
C1
0.1µF
LTC1428-50
3
4
SHDN
CLK
GND
CS
6
5
U
U
U
1
LTC1428-50
ABSOLUTE
MAXIMUM
RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW
I
OUT
1
V
CC
2
SHDN 3
CLK 4
8 D
OUT
7 D
IN
(UP/DN)
6 GND
5 CS
Supply Voltage (V
CC
) ................................................ 7V
Input Voltage (All Inputs)............ – 0.3V to (V
CC
+ 0.3V)
Output Voltage
I
OUT
...................................................... – 0.3V to 10V
D
OUT
....................................... – 0.3V to (V
CC
+ 0.3V)
Short-Circuit Duration (All Outputs) ............... Indefinite
Operating Temperature Range .................... 0°C to 70°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1428CS8-50
S8 PART MARKING
14285
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 130°C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
V
CC
I
CC
Supply Current
DAC Resolution
DAC Full-Scale Current
DAC Zero-Scale Current
DAC Differential
Nonlinearity
Supply Voltage Rejection
Output Voltage Rejection
I
OUT
Bias Voltage = 2.5V
CONDITIONS
V
CC
= 3.3V, T
A
= 25°C, unless otherwise specified.
MIN
q
TYP
130
0.2
8
MAX
6.5
225
10
51.5
52.5
200
±0.9
UNITS
V
µA
µA
Bits
µA
µA
nA
LSB
LSB
LSB
LSB
µA
V
V
3.0
V
SHDN
= V
DIN
= V
CS
= V
CC
, V
CLK
= 0V, D
OUT
= NC, I
OUT
= NC
Shutdown
q
q
q
48.5
47.5
50
50
I
OUT
Bias Voltage = 2.5V
Monotonicity Guaranteed, No Missing Codes
V
CC
= 3V to 6.5V, Full Scale Current, I
OUT
Bias Voltage = 2.5V
V
CC
= 5V, Full Scale Current,
2V
≤
V(I
OUT
)
≤
3V
V
CC
= 5V, Full Scale Current,
3V
≤
V(I
OUT
)
≤
10V
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
±1
±4
±1
±1
±4
±1
Logic Input Current
V
IH
V
IL
V
OH
V
OL
I
OZ
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
0V
≤
V
IN
≤
V
CC
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V, I
O
= 400µA
V
CC
= 3.3V, I
O
= 400µA
V
CC
= 5V, I
O
= 2mA
V
CC
= 3.3V, I
O
= 1mA
2.0
1.9
0.80
0.45
2.4
2.1
0.4
0.4
±5
Three-State Output Leakage V
CS
= V
CC
2
U
W
U
U
W W
W
V
V
V
V
V
V
µA
LTC1428-50
RECO
f
CLK
t
CKS
t
CSS
t
DV
t
DS
t
DH
t
DO
t
CKHI
t
CKLO
t
CSH
t
DZ
t
CKH
t
CSLO
t
CSHI
E DED OPERATI G CO DITIO S
CONDITIONS
SYMBOL PARAMETER
Serial Interface
Clock Frequency
Setup Time, CLK↓ Before CS↓
Setup Time, CS↓ Before CLK↑
CS↓ to D
OUT
Valid
D
IN
Setup Time Before CLK↑
D
IN
Hold Time After CLK↑
CLK↓ to D
OUT
Valid
CLK High Time
CLK Low Time
CLK↓ Before CS↑
CS↑ to D
OUT
in Hi-Z
CS↑ Before CLK↑
CS Low Time
CS High Time
See Test Circuits
See Test Circuits
See Test Circuits
f
CLK
= 2MHz (Note 4)
V
CLK
= 0V
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2:
Timing for all input signals is measured at 0.8V for a High-to-Low
transition and at 2V for a Low-to-High transition.
Note 3:
Timing specifications are guaranteed by design but not tested.
Note 4:
This is the minimum time required for valid data transfer.
TYPICAL PERFORMANCE CHARACTERISTICS
DNL vs Code
1.0
0.8
0.6
0.4
V
CC
= 3.3V
V(I
OUT
) = 2.5V
T
A
= 25°C
1.0
0.8
0.6
0.4
INL (LSB)
∆FULL-SCALE
OUTPUT CURRENT (LSB)
INL vs Code
V
CC
= 3.3V
V(I
OUT
) = 2.5V
T
A
= 25°C
2.0
1.5
1.0
0.5
0
– 0.5
– 1.0
– 1.5
– 2.0
DNL (LSB)
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
0
32
64
96 128 160 192 224 256
CODE
1428-50 G01
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32
64
96 128 160 192 224 256
CODE
1428-50 G02
U
U
U
U W
U WW
V
CC
= 5V, unless otherwise specified. (Notes 2, 3)
MIN
q
q
q
q
q
q
q
q
q
q
q
q
q
q
TYP
MAX
2
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
400
150
150
150
150
200
250
150
400
400
4550
400
400
ns
ns
ns
ns
ns
Supply Voltage Rejection
V(I
OUT
) = 2.5V
T
A
= 25°C
1
2
5
4
SUPPLY VOLTAGE (V)
3
6
7
1428-50 G03
3
LTC1428-50
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Variation
52.5
∆FULL-SCALE
OUTPUT CURRENT (LSB)
FULL-SCALE OUTPUT CURRENT (µA)
V
CC
= 3.3V
V(I
OUT
) = 2.5V
–2
–4
ZERO-SCALE CURRENT (nA)
51.5
50.5
49.5
48.5
47.5
– 55
– 25
35
65
95
5
TEMPERATURE (°C)
PIN FUNCTIONS
I
OUT
(Pin 1):
DAC Current Sink Output. In 3.3V or 5V
systems, the DAC I
OUT
pin can be biased from 2V to 10V.
V
CC
(Pin 2):
Voltage Supply (3V
≤
V
CC
≤
6.5V). This supply
must be kept free from noise and ripple by bypassing
directly to a ground plane.
SHDN (Pin 3):
Shutdown. A logic low puts the chip
into shutdown mode. The digital setting for the DAC is
retained.
CLK (Pin 4):
Shift Clock. This clock synchronizes the serial
data and has a Schmitt trigger input.
CS (Pin 5):
Chip Select Input. In 3-wire mode, a logic low
enables the LTC1428-50. Upon power-up, a logic high
puts the chip into pulse mode. If CS ever goes low, the chip
is configured into 3-wire mode until V
CC
is reset.
GND (Pin 6):
Ground. Ground should be tied directly to a
ground plane.
D
IN
(UP/DN)(Pin 7):
Data Input. In 3-wire mode, the DAC
data is shifted into D
IN
. In pulse mode, upon power-up a
logic high puts the counter into increment-only mode. If
D
IN
ever goes low, the counter is configured in increment/
decrement mode until V
CC
is reset.
D
OUT
(Pin 8):
Data Output. In 3-wire mode, on every
conversion D
OUT
serially outputs the previous 8-bit DAC
data. In pulse mode, D
OUT
is three-stated.
4
U W
125
1428-50 G04
Bias Voltage Rejection
2
0
0.06
ZERO-SCALE OUTPUT CURRENT (LSB)
0.05
0.04
0.03
–6
–8
–10
–12
155
Zero-Scale I
OUT
vs Temperature
20
18
16
14
12
10
8
6
4
2
0
0
10
40
30
20
50
TEMPERATURE (°C)
60
70
V(I
OUT
) = 5V
V(I
OUT
) = 2.5V
V(I
OUT
) = 10V
V
CC
= 3.3V
0.02
0.01
0
0
2
4
12
I
OUT
BIAS VOLTAGE (V)
6
8
10
14
16
V
CC
= 3.3V
T
A
= 25°C
1428-50 G05
1428-50 G06
U
U
U
LTC1428-50
BLOCK DIAGRA
POWER-ON
RESET
CLK
D
IN
CS
SHDN
CONTROL
LOGIC
TEST CIRCUITS
Load Circuit for t
DO
1.4V
3k
D
OUT
100pF
1428-50 TC01
Voltage Waveforms for t
DO
CLK
0.8V
t
DO
D
OUT
2.4V
0.4V
1428-50 TC03
W
LATCH
AND
LOGIC
UP ONLY/
UP/DN
VOLTAGE
REFERENCE
SHDN
LATCH
AND
LOGIC
MODE SELECT
0 = PULSE
1 = SPI
SHDN
8-BIT
CURRENT
DAC
I
OUT
8
CLK
8-BIT REGISTER/COUNTER
UP/DN
8
8
CLK
9-BIT SHIFT REGISTER
D
OUT
(LSB)
Q9
D
OUT
1428-50 BD
Load Circuit for t
DZ,
t
DV
3k
D
OUT
100pF
5V t
DZ
WAVEFORM 2, t
DV
t
DZ
WAVEFORM 1
1428-50 TC02
Voltage Waveforms for t
DZ
, t
DV
CS
2.0V
0.8V
D
OUT
WAVEFORM 1
(SEE NOTE 1)
D
OUT
WAVEFORM 2
(SEE NOTE 2)
2.4V
t
DZ
90%
t
DV
0.4V
10%
1428-50 TC04
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS
DISABLED BY CS
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS
DISABLED BY CS
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