LTC1661
Micropower Dual
10-Bit DAC in MSOP
FEATURES
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DESCRIPTION
The LTC
®
1661 integrates two accurate, serially address-
able, 10-bit digital-to-analog converters (DACs) in a single
tiny MS8 package. Each buffered DAC draws just 60µA
total supply current, yet is capable of supplying DC output
currents in excess of 5mA and reliably driving capacitive
loads up to 1000pF Sleep mode further reduces total
.
supply current to a negligible 1µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneous update capability and can be used to write
to either DAC without interrupting sleep mode.
Ultralow supply current, power-saving sleep mode and
extremely compact size make the LTC1661 ideal for
battery-powered applications, while its straightforward
usability, high performance and wide supply range make
it an excellent choice as a general purpose converter.
For additional outputs and even greater board density,
please refer to the LTC1660 micropower octal DAC for
10-bit applications. For 8-bit applications, please consult
the LTC1665 micropower octal DAC.
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Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Board Space of an SO-8
Micropower: 60µA per DAC
Sleep Mode: 1µA for Extended Battery Life
Rail-to-Rail Voltage Outputs Drive 1000pF
Wide 2.7V to 5.5V Supply Range
Double Buffered for Independent or Simultaneous
DAC Updates
Reference Range Includes Supply for Ratiometric
0V-to-V
CC
Output
Reference Input Has Constant Impedance over All
Codes (260kΩ Typ)—Eliminates External Buffers
3-Wire Serial Interface with Schmitt Trigger Inputs
Differential Nonlinearity: ≤±0.75LSB Max
APPLICATIONS
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Mobile Communications
Digitally Controlled Amplifiers and Attenuators
Portable Battery-Powered Instruments
Automatic Calibration for Manufacturing
Remote Industrial Devices
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
V
OUT A
8
GND
7
V
CC
6
V
OUT B
5
Differential Nonlinearity (DNL)
0.75
LATCH
LATCH
LATCH
10-BIT
DAC A
LATCH
10-BIT
DAC B
0.60
0.40
0.20
LSB
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
0
–0.20
–0.40
–0.60
–0.75
0
256
512
CODE
768
1023
1661 G02
1661 BD
1
CS/LD
2
SCK
3
D
IN
4
REF
1661fa
1
LTC1661
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V
CC
to GND .............................................. –0.3V to 7.5V
Logic Inputs to GND ............................... –0.3V to 7.5V
V
OUT A
, V
OUT B
, REF to GND ...........–0.3V to V
CC
+ 0.3V
Maximum Junction Temperature...........................125°C
Storage Temperature Range.................. –65°C to 150°C
Operating Temperature Range
LTC1661C ............................................... 0°C to 70°C
LTC1661I ............................................ –40°C to 85°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
CS/LD
SCK
D
IN
REF
1
2
3
4
8
7
6
5
V
OUT A
GND
V
CC
V
OUT B
CS/LD
1
SCK 2
D
IN
3
REF 4
8
7
6
5
V
OUT A
GND
V
CC
V
OUT B
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 150°C/W
N8 PACKAGE
8-LEAD PLASTIC DIP
T
JMAX
= 150°C,
θ
JA
= 100°C/W
ORDER INFORMATION
LEAD FREE FINISH
LTC1661CMS8#PBF
LTC1661IMS8#PBF
LTC1661CN8#PBF
LTC1661IN8#PBF
TAPE AND REEL
LTC1661CMS8#TRPBF
LTC1661IMS8#TRPBF
LTC1661CN8#TRPBF
LTC1661IN8#TRPBF
PART MARKING
LTDV
LTDW
LTC1661CN8
LTC1661IN8
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic DIP
8-Lead Plastic DIP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL
Accuracy
Resolution
Monotonicity
DNL
INL
V
OS
FSE
PSR
Differential Nonlinearity
Integral Nonlinearity
Offset Error
V
OS
Temperature Coefficient
Full-Scale Error
Full-Scale Error Temperature Coefficient
Power Supply Rejection
PARAMETER
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
REF
≤ V
CC
, V
OUT
unloaded unless otherwise noted.
CONDITIONS
l
MIN
10
10
TYP
MAX
UNITS
Bits
Bits
1V ≤ V
REF
≤ V
CC
– 0.1V (Note 2)
1V ≤ V
REF
≤ V
CC
– 0.1V (Note 2)
1V ≤ V
REF
≤ V
CC
– 0.1V (Note 2)
Measured at Code 20
V
CC
= 5V, V
REF
= 4.096V
V
REF
= 2.5V
l
l
l
l
±0.1
±0.4
±5
±15
±1
±30
0.18
±0.75
±2
±30
±12
LSB
LSB
mV
µV/°C
LSB
µV/°C
LSB/V
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l
2
LTC1661
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
Input Voltage Range
Resistance
Capacitance
I
REF
V
CC
I
CC
Reference Current
Positive Supply Voltage
Supply Current
Sleep Mode
For Specified Performance
V
CC
= 5V (Note 3)
V
CC
= 5V (Note 3)
Sleep Mode (Note 3)
V
OUT
= 0V, V
CC
= V
REF
= 5V, Code = 1023
V
OUT
= V
CC
= V
REF
= 5V, Code = 0
Rising (Notes 4, 5)
Falling (Notes 4, 5)
To ±0.5LSB (Notes 4, 5)
Power Supply
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
REF
≤ V
CC
, V
OUT
unloaded unless otherwise noted.
CONDITIONS
l
MIN
0
140
TYP
MAX
V
CC
UNITS
V
kΩ
pF
Reference Input
Active Mode
l
l
l
260
15
0.001
1
5.5
120
95
1
195
154
3
100
120
µA
V
µA
µA
µA
mA
mA
V/µs
V/µs
µs
pF
V
V
2.7
DC Performance
Short-Circuit Current Low
Short-Circuit Current High
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
Capacitive Load Driving
Digital I/O
V
IH
V
IL
I
LK
C
IN
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Leakage
Digital Input Capacitance
V
CC
= 2.7V to 5.5V
V
CC
= 2.7V to 3.6V
V
CC
= 4.5V to 5.5V
V
CC
= 2.7V to 5.5V
V
IN
= GND to V
CC
(Note 6)
l
l
l
l
l
l
l
l
10
7
25
19
0.60
0.25
30
1000
2.4
2.0
0.8
0.6
±10
10
V
V
µA
pF
TIMING CHARACTERISTICS
range, otherwise specifications are at T
A
= 25°C.
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
9
t
11
PARAMETER
D
IN
Valid to SCK Setup
D
IN
Valid to SCK Hold
SCK High Time
SCK Low Time
CS/LD
Pulse Width
LSB SCK High to
CS/LD
High
CS/LD
Low to SCK High
SCK Low to
CS/LD
Low
CS/LD
High to SCK Positive Edge
SCK Frequency
V
CC
= 4.5V to 5.5V
The
l
denotes the specifications which apply over the full operating temperature
CONDITIONS
l
l
MIN
40
0
30
30
80
30
20
0
20
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
Square Wave (Note 6)
l
l
l
l
l
l
l
l
16.7
MHz
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3
LTC1661
TIMING CHARACTERISTICS
range, otherwise specifications are at T
A
= 25°C.
PARAMETER
D
IN
Valid to SCK Setup
D
IN
Valid to SCK Hold
SCK High Time
SCK Low Time
CS/LD
Pulse Width
LSB SCK High to
CS/LD
High
CS/LD
Low to SCK High
SCK Low to
CS/LD
Low
CS/LD
High to SCK Positive Edge
SCK Frequency
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
9
t
11
V
CC
= 2.7V to 5.5V
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
Square Wave (Note 6)
l
l
l
l
l
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating temperature
CONDITIONS
MIN
60
0
50
50
100
50
30
0
30
10
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Nonlinearity and monotonicity are defined from code 20 to code
1023 (full scale). See Applications Information.
Note 3:
Digital inputs at 0V or V
CC
.
Note 4:
Load is 10kΩ in parallel with 100pF.
Note 5:
V
CC
= V
REF
= 5V. DAC switched between 0.1V
FS
and 0.9V
FS
,
i.e., codes k = 102 and k = 922.
Note 6:
Guaranteed by design and not subject to test.
TIMING DIAGRAM
t
1
t
2
SCK
t
9
D
IN
t
5
CS/LD
1661 TD
t
3
t
4
t
6
t
11
A3
t
7
A2
A1
X1
X0
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LTC1661
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
2.0
1.5
1.0
0.5
LSB
LSB
0
–0.5
–1.0
–1.5
–2.0
0
256
512
CODE
768
1023
1661 G01
Differential Nonlinearity (DNL)
0.75
0.60
0.40
0.20
0
–0.20
–0.40
–0.60
–0.75
0
256
512
CODE
768
1023
1661 G02
Minimum Supply Headroom vs
Load Current (Output Sourcing)
1400
1200
1000
V
CC
– V
OUT
(mV)
800
600
–55°C
400
200
0
V
REF
= 4.096V
∆V
OUT
< 1LSB
CODE = 1023
125°C
25°C
0
2
|
I
OUT
|
(mA) (Sourcing)
4
6
8
10
1661 G03
Minimum V
OUT
vs Load Current
(Output Sinking)
1400
1200
1000
V
OUT
(mV)
V
OUT
(V)
800
600
400
200
0
25°C
–55°C
V
CC
= 5V
CODE = 0
125°C
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
0
2
4
6
8
10
1661 G04
Mid-Scale Output Voltage
vs Load Current
V
REF
= V
CC
CODE = 512
V
CC
= 5.5V
V
OUT
(V)
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
SOURCE
–20
–10
SINK
20
30
1661 G05
Mid-Scale Output Voltage
vs Load Current
V
REF
= V
CC
CODE = 512
V
CC
= 3.6V
V
CC
= 3V
V
CC
= 5V
V
CC
= 4.5V
V
CC
= 2.7V
1.0
–15 –12
–8
SOURCE
SINK
8
12 15
1661 G06
|
I
OUT
|
(mA) (SINKING)
–30
0
10
I
OUT
(mA)
–4
0
4
I
OUT
(mA)
Load Regulation
vs Output Current
2.0
1.5
1.0
∆V
OUT
(LSB)
∆V
OUT
(LSB)
0.5
0
–0.5
–1.0
–1.5
–2.0
–2
SOURCE
–1
0
I
OUT
(mA)
SINK
1
2
1661 G07
Load Regulation
vs Output Current
2.0
1.5
1.0
V
OUT
(V)
0.5
0
–0.5
–1.0
–1.5
–2.0
–500
SOURCE
0
I
OUT
(µA)
SINK
500
1661 G08
Large-Signal Step Response
5
V
CC
= V
REF
= 5V
10% TO
CODE = 922
90% STEP
V
CC
= V
REF
= 5V
CODE = 512
V
CC
= V
REF
= 3V
CODE = 512
4
3
2
1
0
CODE = 102
0
20
40
60
TIME (µs)
80
100
1661 G09
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FPGA/CPLD
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