DICE/DWF SPECIFICATION
RH1056
Precision, High Speed, JFET
Input Operational Amplifier
1
7
DIE CROSS REFERENCE
(Notes 1 and 2)
LTC Finished
Part Number
6
2
Order DICE CANDIDATE
Part Number Below
RH1056 DICE
RH1056 DWF*
RH1056A
RH1056A
Please refer to LTC standard product data sheet for
other applicable product information.
*DWF = DICE in wafer form.
PAD FUNCTION
3
4
5
59mils
×
78mils,
Backlap: 12mils
Backside (substrate) is an alloyed gold layer.
1.
2.
3.
4.
5.
6.
7.
BALANCE
– IN
+ IN
V
–
BALANCE
OUT
V
+
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
DICE ELECTRICAL TEST LIMITS
(Note 3)
SYMBOL
V
OS
I
OS
I
B
A
VOL
PARAMETER
Input Offset Voltage
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
CONDITIONS
(Note 3)
(Note 4)
(Note 4)
V
O
= ±10V, R
L
= 2k
120
MIN
MAX
0.5
50
200
UNITS
mV
pA
pA
V/mV
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
DICE/DWF SPECIFICATION
RH1056
DICE ELECTRICAL TEST LIMITS
(Note 3)
SYMBOL
V
OUT
CMRR
PSRR
SR
I
S
PARAMETER
Output Voltage Swing
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Slew Rate
Supply Current
CONDITIONS
R
L
= 2k, V
S
= ±15V
V
CM
= ±11V, V
S
= ±15V
VS = ±10V to ±18V
(Note 5)
MIN
±12
86
88
10
6
MAX
UNITS
V
dB
dB
V/μs
mA
Note 1:
Dice are probe tested at 25°C to the limits shown. Final specs,
after assembly cannot be guaranteed at the die level due to yield loss and
assembly shifts. For absolute maximum ratrings, typical specifications,
performance curves and finished product specifications, please refer to the
standard product data sheet.
Note 2:
For dice tested to tighter limits than those listed above and/or, lot
qualification based on sample lot assembly and testing, please contact LTC
Marketing.
Note 3:
V
S
= ±15V, T
A
= 25°C, V
CM
= 0
V
, unless otherwise noted.
Note 4:
This is not a reflection of actual I
OS
and I
B
. Typical values are 5pA
and 20pA respectively at final test. JFETs sensitivity to light at wafer sort
requires a loose limit.
Note 5:
Tested at a gain of “5”.
Rad Hard die require special handling as compared to standard IC chips.
Rad Hard die are susceptible to surface damage because there is no silicon
nitride passivation as on standard die. Silicon nitride protects the die surface
from scratches by its hard and dense properties. The passivation on Rad Hard
die is silicon dioxide that is much “softer” than silicon nitride.
LTC recommends that die handling be performed with extreme care so
as to protect the die surface from scratches. If the need arises to move
the die around from the chip tray, use a Teflon-tipped vacuum wand.
This wand can be made by pushing a small diameter Teflon tubing onto the
tip of a steel-tipped wand. The inside diameter of the Teflon tip should match
the die size for efficient pickup. The tip of the Teflon should be cut square
and flat to ensure good vacuum to die surface. Ensure the Teflon tip remains
clean from debris by inspecting under stereoscope.
During die attach, care must be exercised to ensure no tweezers touch the
top of the die.
Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information
on dice performance and lot qualifications via lot sampling test procedures.
Dice data sheet subject to change. Please consult factory for current revision in production.
I.D.No. 66-13-1056
2
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX:
(408) 434-0507
●
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