AN4243
Application note
The L6230 DMOS driver for three-phase brushless DC motor
By Cristiana Scaramel
Introduction
Modern motion control applications need more flexibility that can be only addressed with
specialized ICs products. The L6230 is a DMOS fully integrated three-phase BLDC motor
driver optimized for field oriented control (FOC) application thanks to the independent
current senses. The device integrates six DMOS power transistors with CMOS and bipolar
circuits on the same chip including overcurrent protection for safe operation and flexibility.
An uncommitted comparator with open-drain output for optional function is available.
January 2013
Doc ID 024199 Rev 1
1/29
www.st.com
Contents
AN4243
Contents
1
2
L6230 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Designing an application with the L6230 . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Current ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Voltage ratings and operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Choosing the bulk capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sensing resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Charge pump external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Sharing the charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
How to generate a reference voltage for the current control . . . . . . . . . . 12
Input logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Brake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
3.2
3.3
Field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . 23
Six-step driving method with BEMF zero crossing detection . . . . . . . . . . 24
4
Demonstration boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
4.2
EVAL6230QR demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STEVAL-IFN003V1:PMSM FOC motor driver based on the L6230
and STM32F103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3
STEVAL-IFN004V1:BLDC six-step motor driver based on the L6230
and STM8S105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
Doc ID 024199 Rev 1
AN4243
L6230 block diagram
1
L6230 block diagram
The L6230 (see
Figure 1)
includes logic for CMOS/TTL interface, a charge pump that
provides auxiliary voltage to drive the high-side DMOS, non-dissipative overcurrent
protection circuitry on the high-side DMOS, with a fixed trip point set at 2.8 A (see
Section 2.10),
overtemperature protection, undervoltage lockout for reliable startup.
Figure 1.
L6230 block diagram
V
BOOT
CHARGE
PUMP
THERMAL
PROTECTION
OCD1
OCD1
OCD
DIAG-EN
OCD2
OCD3
V
BOOT
SENSE
1
10V
OUT1
VBOOT
VCP
V
BOOT
VS
A
OCD2
IN
1
EN
1
IN
2
EN
2
IN
3
EN
3
10V
5V
OCD3
10V
VOLTAGE
REGULATOR
V
BOOT
GATE
LOGIC
10V
OUT2
SENSE
2
VS
B
OUT3
SENSE
3
CPOUT
+
-
COMPARATOR
CP+
CP-
AM16563v1
Doc ID 024199 Rev 1
3/29
Designing an application with the L6230
AN4243
2
2.1
Designing an application with the L6230
Current ratings
With MOSFET (DMOS) devices, unlike bipolar transistors, the current under short-circuit
conditions is, at first approximation, limited by the R
DS(on)
of the DMOS themselves and
could reach very high values.
The L6230 OUT pins and the two V
SA
and V
SB
pins are rated for a maximum of 1.4 A r.m.s
and 2.8 A peak (typical values). These values are meant to avoid damaging metal
structures, including the metallization on the die and bond wires.
In practical applications, maximum allowable current is less than these limits; actually the
constraint is the power dissipation. The device integrates overcurrent detection (OCD) that
provides protection against short-circuits between the outputs and between an output and
ground (see
Section 2.10).
2.2
Voltage ratings and operating range
The L6230 requires a single supply voltage (V
S
), for the motor supply. Internal voltage
regulators provide the 5 V and 10 V required for the internal circuitry.
The operating range for V
S
is from 8 to 52 V. To prevent from working into undesirable low
voltage supply an undervoltage lockout (UVLO), circuit shuts down the device when supply
voltage falls below 6 V; to resume normal operating conditions, V
S
must then exceed 6.8 V.
The hysteresis is provided to avoid false intervention of the UVLO function during fast V
S
ringings.
It should be noted, however, that DMOS's R
DS(on)
is a function of the V
S
supply voltage.
Actually, when V
S
is less than 10 V, R
DS(on)
is adversely affected, and this is particularly true
for the high-side DMOS that are driven from VBOOT supply. This supply is obtained through
a charge pump from the internal 10 V supply, which tends to reduce its output voltage when
V
S
goes below 10 V.
Figure 2
shows the supply voltage of the high-side gate drivers
(VBOOT - V
S
) versus the supply voltage (V
S
).
Figure 2.
Supply voltage of high-side gate drivers versus supply voltage
4/29
Doc ID 024199 Rev 1
AN4243
Designing an application with the L6230
Note that V
S
must be connected to both V
SA
and V
SB
since the bootstrap voltage (at
VBOOT pin) is the same as the three half-bridges. The integrated DMOS have a rated drain-
source breakdown voltage of 60 V. However V
S
should be kept below 52 V, since, in normal
working conditions, the DMOS see a V
ds
voltage that exceeds the V
S
supply. In particular,
when a high-side DMOS turns off due to a phase change (OUT1 in
Figure 3),
if one of the
other outputs (OUT2 in
Figure 3)
is high, the load current starts flowing in the low-side
freewheeling diode and the SENSE pin sees a negative spike due to a non-negligible
parasitic inductance of the PCB path from the pin to GND. This spike is followed by a stable
negative voltage due to the drop on R
SENSE
. The OUT pin sees a similar behavior, but with
a slightly larger voltage due to the forward recovery time of the integrated freewheeling
diode and the forward voltage drop across it. Typical duration of this spike is 30 ns. At the
same time, the OUT2 pin (in the example of
Figure 3)
sees a voltage above V
S
, due to
voltage drop across the high-side (integrated) freewheeling diode, as the current reverses
direction and flows into the bulk capacitor. It turns out that the highest differential voltage is
observed between two OUT pins when a phase change turns a high-side off, and this must
always be kept below 60 V.
Figure 3.
Currents and voltages if a phase change turns a high-side off during off-
time
Current
starts
flowing in the third
half
bridge
Bulk
Capacitor
Equivalent
Circuit
ESR
ESL
PCB Parasi c
Inductance
V
S
R
SENSE
*I+V
F(Diode)
R
SENSE
*I
CB
Parasi c
Inductance
on- me
off- me
during off- me
a
phase change can occur
AM16565v1
Figure 4
shows the voltage waveforms at the OUT pins referring to a possible practical
situation, with a peak output current of 1.4 A, V
S
= 52 V, R
SENSE
= 0.33
Ω
T
J
= 25 ºC
,
(approximately) and a good PCB layout.
Below ground spike amplitude is -2.65 V for one output, the other OUT pin is at about 55 V.
In these conditions, total differential voltage reaches almost 60 V, which is the absolute
maximum rating for the DMOS. Keeping differential voltage between two output pins within
rated values is a must that can be accomplished with proper selection of bulk capacitor
value and equivalent series resistance (ESR), according to the current peaks and adopting
good layout practices to minimize PCB parasitic inductances.
Doc ID 024199 Rev 1
5/29
测试/测量
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
