AN2476
Application note
STR75x low power modes
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the low power modes of the STR75x product family. It describes
how to use the STR75x product family and details the components of supply circuitry, clock
systems, register settings and low power management in order to optimize the use of
STR750 in applications where low power is key.
July 2007
Rev 2
1/49
www.st.com
Contents
AN2476
Contents
1
Power supply and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
1.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1
1.3.2
1.3.3
1.3.4
Power scheme 1: single external 3.3V power source . . . . . . . . . . . . . . . 5
Power scheme 2: dual external 3.3V and 1.8V power sources . . . . . . . . 7
Power scheme 3: single external 5.0V power source . . . . . . . . . . . . . . . 8
Power scheme 4: dual external 5.0V and 1.8V power sources . . . . . . . . 9
1.4
1.5
1.6
1.7
Main voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low power voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Regulator startup monitor (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7.1
1.7.2
Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Peripheral clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.8.1
1.8.2
1.8.3
1.8.4
1.8.5
1.8.6
1.8.7
Low power bit writing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SLOW mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCG mode: peripherals clocks gated mode . . . . . . . . . . . . . . . . . . . . . 16
WFI mode: Wait For Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Auto-Wake-Up (AWU) from low power mode . . . . . . . . . . . . . . . . . . . . . 25
2
STR750 library low power mode functions . . . . . . . . . . . . . . . . . . . . . . 26
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
MRCC_CKSYSConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MRCC_HCLKConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MRCC_CKTIMConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MRCC_PCLKConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MRCC_EnterWFIMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MRCC_EnterSTOPMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MRCC_EnterSTANDBYMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MRCC_PeripheralClockConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/49
AN2476
Contents
3
Operating measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1
Setup board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.1
3.1.2
Measurement with STR750_EVAL Board . . . . . . . . . . . . . . . . . . . . . . . 33
Measurements with Uniboard QFP 100 in single supply (3.3V or 5V) . . 34
3.2
Software provided with this application note . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1
3.2.2
3.2.3
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
WFI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
Measurement and typical value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4
5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
Power supply and clocks
AN2476
1
1.1
Power supply and clocks
Introduction
The device can be connected in any of the following schemes, depending on the application
requirements:
●
●
●
●
Power scheme 1: Single external 3.3V power source
Power scheme 2: Dual external 3.3V and 1.8V power sources
Power scheme 3: Single external 5.0V power source
Power scheme 4: Dual external 5.0V and 1.8V power sources
1.2
Power supplies
The device has five power pins:
●
V
DD_IO
: power supply for I/Os (3.3V ±0.3V or 5V ±0.5V). Must be kept on, even in
STANDBY mode.
V
18
(pins V
18REG
and V
18
which are internally shorted): Power Supply for Digital,
SRAM and Flash: 1.8V ± 0.15V.
V
18_BKP
: Backup Power Supply for STANDBY or STOP Mode
Two embedded regulators are available to supply the internal 1.8V digital power:
●
●
V
18
and V
18_BKP
are normally generated internally by the embedded regulators:
The Main Voltage Regulator (MVREG) supplies V
18
and V
18_BKP
. It delivers a power supply
of 1.8V.
The Low Power Voltage Regulator (LPVREG) can supply V
18_BKP
or V
18
in STOP or
STANDBY mode (see
Section 1.8: Low power modes on page 14).
It delivers a power
supply of 1.6V ± 0.2V.
When the embedded regulators are used, the Main Digital part of the chip (V
18
) can be
powered off (meaning V
18
left hi-Z) while keeping the backup circuitry powered on
(V
18_BKP
).
It is also possible to supply V
18
and V
18_BKP
externally.
Two sensitive analog blocks have dedicated power pins:
●
●
V
DDA_PLL
: Analog Power supply for PLL (must have the same voltage level as V
DD_IO
)
V
DDA_ADC
: Analog Power supply for ADC (must have the same voltage level as V
DD_IO
)
4/49
AN2476
Power supply and clocks
1.3
1.3.1
Power supply schemes
Power scheme 1: single external 3.3V power source
In this configuration, the internal voltage regulators are switched on by forcing the
VREG_DIS pin to low level. The V
CORE
supply required for the kernel logic and the V
BACKUP
supply required for the backup circuitry are generated internally by the Main Voltage
Regulator or the Low Power Voltage Regulator (depending on the selected low power
mode). This scheme has the advantage of requiring only one power source. Refer to
Figure 1 on page 5.
At power-up and during
NORMAL
mode (all operating modes except STOP and STANDBY
Modes):
●
●
The Main Voltage Regulator powers both V
CORE
supply required for the kernel logic
and the V
BACKUP
supply required for the backup circuitry.
The Low Power Regulator is not used
Power supply scheme 1 (single 3.3V supply VREGDIS=0) in NORMAL
mode
Figure 1.
V
18_BKP
1µF
V
SS_BKP
VREG_DIS
V
18
33nF
V
SS18
V
18REG
10µF
V
SS18
V
DD_IO
3.3V
+/-0.3V
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
NORMAL
MODE
V
BACKUP
LOW POWER
V
LPVREG
~1.4V
VOLTAGE
REGULATOR
POWER
SWITCH
V
18
BACKUP
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
1µF
V
SS_IO
MAIN
V
MVREG
= 1.8V
VOLTAGE
REGULATOR
V
IO
=3.3V
OUT
V
CORE
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
GP I/Os
IN
I/O LOGIC
V
DD_PLL
V
SS_PLL
3.3V
PLL
V
DD_ADC
3.3V
V
SS_ADC
ADC
IN
ADC
5/49
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
