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TNETE2201
1.25-GIGABIT ETHERNET TRANSCEIVER
SLLS267D – JUNE 1997 – REVISED FEBRUARY 1999
D
D
D
D
D
1.25 Gigabits Per Second (Gbps) Gigabit
Ethernet Transceiver
Based On the P802.3Z Specification
Transmits Serial Data Up to 1.25 Gbps
Operates With 3.3-V Supply Voltage
5-V Tolerant on TTL Inputs
D
D
D
D
D
Interfaces to Electrical Cables/Backplane or
with Optical Modules
PECL Voltage Differential Signaling Load,
1 V Typ with 50
Ω
– 75
Ω
Receiver Differential Input Voltage
200 mV Minimum
Low Power Consumption
64-Pin Quad Flat Pack With Thermally
Enhanced Package
description
The TNETE2201 Gigabit Ethernet transceiver provides for ultra high-speed bidirectional point-to-point data
transmission. This device is based on the timing requirements of the proposed 10-bit interface specification by
the P802.3z Gigabit Task Force.
PHD OR PJD PACKAGE
(TOP VIEW)
GND_A
V
CC
_A
DOUT_TXP
DOUT_TXN
V
CC
_A
V
CC
_A
GND_CMOS
V
CC
_A
GND_A
V
CC
_A
DIN_RXP
V
CC
_A
DIN_RXN
GND_RX
GND_CMOS
TD0
TD1
TD2
V
CC
_CMOS
TD3
TD4
TD5
TD6
V
CC
_CMOS
TD7
TD8
TD9
GND_CMOS
GND_TX
TC1
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
CC
_RX
RC1
RC0
SYNC
GND_TTL
RD0
RD1
RD2
V
CC
_TTL
RD3
RD4
RD5
RD6
V
CC
_TTL
RD7
RD8
RD9
GND_TTL
Copyright
©
1999, Texas Instruments Incorporated
10
11
12
13
14
15
33
16
1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TC0
V
CC
_TX
LOOPEN
V
CC
_A
GND_A
REFCLK
V
CC
_CMOS
SYNCEN
GND_CMOS
RESERVED
LCKREFN
V
CC
_A
V
CC
_A
RBC1
RBC0
GND_A
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TNETE2201
1.25-GIGABIT ETHERNET TRANSCEIVER
SLLS267D – JUNE 1997 – REVISED FEBRUARY 1999
description (continued)
The intended application of this device is to provide building blocks for developing point-to-point baseband data
transmission over controlled-impedance media of approximately 50
Ω
to 75
Ω.
The transmission media can be
printed-circuit board traces, back planes, cables, or fiber-optical media. The ultimate rate and distance of data
transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The TNETE2201 performs the data serialization and deserialization (SERDES) functions for the gigabit
ethernet physical layer interface. The transceiver operates at 1.25 Gbps (typical), providing up to 1000 Mbps
of bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel
encoded data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero
(NRZ) at pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input
serial stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output
with respect to two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the parallel bytes in
RBC clock rising edges.
The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver
can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.
The TNETE2201 provides an internal loopback capability for self-test purposes. Serial data from the serializer
is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.
The TNETE2201 is characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TNETE2201
1.25-GIGABIT ETHERNET TRANSCEIVER
SLLS267D – JUNE 1997 – REVISED FEBRUARY 1999
functional block diagram
LOOPEN
TX+
TX–
TD0 – TD9
10
/
10-Bit
Register
10
/
Shift
Register
REFCLK
125 MHz
Clock
Multiplier
SYNCEN
SYNC
Synchronous
Detect
RD0 – RD9
10
/
10-Bit
Register
10
/
Shift
Register
62.5 MHz
RBC0
RBC1
62.5 MHz
÷
2
125 MHz
PLL Clock
Recovery and
Data Retiming
2:1
MUX
RX+
RX–
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
TNETE2201
1.25-GIGABIT ETHERNET TRANSCEIVER
SLLS267D – JUNE 1997 – REVISED FEBRUARY 1999
I/O structures
PECL inputs (DIN_RXP, DIN_RXN)
VDD
100
Ω
DIN_RXP
4 kΩ
VCM
4 kΩ
DIN_RXN
DOUT_TXN
+
_
VDD
DOUT_TXP
PECL outputs (DIN_TXP, DIN_TXN)
VDD
VDD
CMOS inputs (TD0 – TD9, LOOPEN, REFCLK, SYNCEN, LCKREFN)
VDD
VDD
P
R1
120
Ω
Input
R2
TERMINALS
REFCLK, TD0 – TD9
LOOPEN
SYNCEN, LCKREFN
N
R1
R2
Open Circuit Open Circuit
Open Circuit
400 kΩ
400 kΩ
Open Circuit
CMOS outputs (RD0 – RD9, RBC0, RBC1, SYNC)
VDD
P
Output
N
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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