FINAL
Am28F256
256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
High performance
— 70 ns maximum access time
s
CMOS Low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
s
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
s
10,000 write/erase cycles minimum
s
Write and erase voltage 12.0 V
±5%
s
Latch-up protected to 100 mA
from –1 V to V
CC
+1 V
s
Flasherase Electrical Bulk Chip-Erase
— One second typical chip-erase
s
Flashrite Programming
— 10 µs typical byte-program
— 0.5 second typical chip program
s
Command register architecture for
microprocessor/microcontroller compatible
write interface
s
On-chip address and data latches
s
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s
Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The Am28F256 is a 256 K Flash memory organized as
32 Kbytes of 8 bits each. AMD’s Flash memories offer
the most cost-effective and reliable read/write non-
volatile random access memory. The Am28F256 is
packaged in 32-pin PDIP PLCC, and TSOP versions. It
,
is designed to be reprogrammed and erased in-system
or in standard EPROM programmers. The Am28F256
is erased when shipped from the factory.
The standard Am28F256 offers access times as fast as
70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F256 has separate chip enable (CE
#
) and
output enable (OE
#
) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256 uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.
AMD’s Flash technology reliably stores memor y
contents even after 10,000 erase and program cycles.
Publication#
11560
Rev:
G
Amendment/+2
Issue Date:
January 1998
The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The Am28F256
uses a 12.0V
±
5% V
PP
high voltage input to perform
the Flasherase and Flashrite algorithms.
The highest degree of latch-up protection is achieved
with AMD’s proprietar y non-epi process. Latch-up
protection is provided for stresses up to 100 milliamps
on address and data pins from –1 V to V
CC
+1 V.
The Am28F256 is byte programmable using 10 µs
programming pulses in accordance with AMD’s
Flashrite programming algorithm. The typical room
temperature programming time of the Am28F256 is a
half a second. The entire chip is bulk erased using
10 ms erase pulses according to AMD’s Flasherase
alrogithm. Typical erasure at room temperature is
accomplished in less than one second. The windowed
package and the 15-20 minutes required for EPROM
erasure using ultra-violet light are eliminated.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches ad-
dress and data needed for the programming and erase
operations. For system design simplification, the
Am28F256 is designed to support either WE
#
or CE
#
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of WE
#
or CE
#
whichever occurs last. Data is latched on the rising edge
of WE
#
or CE
#
whichever occurs first. To simplify the fol-
lowing discussion, the WE
#
pin is used as the write cycle
control pin throughout the rest of this text. All setup and
hold times are with respect to the WE
#
signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F256 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
BLOCK DIAGRAM
DQ0–DQ7
VCC
VSS
VPP
Erase
Voltage
Switch
State
Control
To Array
Input/Output
Buffers
WE#
Command
Register
CE#
OE#
Program
Voltage
Switch
Chip Enable
Output Enable
Logic
Data
Latch
Low V
CC
Detector
Program/Erase
Pulse Timer
A0–A14
Y-Decoder
Y-Gating
Address
Latch
X-Decoder
262,144
Bit
Cell Matrix
11560F-1
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options (V
CC
= 5.0 V
±
10%)
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
-70
70
70
35
-90
90
90
35
Am28F256
-120
120
120
50
-150
150
150
55
-200
200
200
55
2
Am28F256
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM28F256
-70
J
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am28F256
256 Kilobit (32 K x 8-Bit) CMOS Flash Memory
Valid Combinations
AM28F256-70
AM28F256-90
AM28F256-120
AM28F256-150
AM28F256-200
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am28F256
5
嵌入式系统
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