AN4308
Application note
Methods of STCC2540, STCC5011, STCC5021 control
By Ondrej Plachy
Introduction
The STCC2540 and STCC5011/STCC5021 (STCCxxxx in text below) devices are
combinations of a current limited USB port power switch with the USB 2.0 high-speed data
line (D+/D-) switch and the USB charging port identification circuit. Applications include
notebook PCs, all-in-one PCs, desktop PCs and other intelligent USB host devices.
The CTL1, CTL2 and CTL3 (CTLx in text below) logic inputs are used to select one of the
various operating modes provided by the STCCxxxx. These modes allow the host device to
actively select between:
“Standard Downstream Port” (SDP) (active USB 3.0 data communication with 900 mA
support or USB 2.0 data communication with 500 mA support)
“Charging Downstream Port” (CDP) (active USB data communication with 1.5 A support)
“Dedicated Charging Port” (DCP) (wall adapter emulation with no data communication
and up to 2.5 A support).
The STCCxxxx devices also integrate the autodetect feature that supports both DCP
schemes for the “Battery Charging Specification” (BC1.2, a maximum current draw of 1.5 A)
enhanced of Korean tablets support and the divider mode (a maximum current draw of 1 A
for the STCC5011 or 2 A for the STCC2540 and STCC5021) without the need for an outside
user interaction.
The STCC5011/STCC5021 (STCC50x1 in text below) devices support the peripheral
attachment detection in the G2/G3 power state and provide charging without the need of
waking up the whole host system. The attachment detection is controlled by a combination
of the EN and ATTACH_EN pins.
This Application note is focused on selecting the STCCxxxx operating mode by various
methods of driving its control inputs (CTLx, EN, ATTACH_EN).
June 2013
DocID024781 Rev 1
1/14
www.st.com
Contents
AN4308
Contents
1
2
Management of CTLx pins to select operating mode . . . . . . . . . . . . . . 3
Application dependent CTLx controlling options . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
CTLx pins controlled by GPIO from embedded controller . . . . . . . . . . . . . 5
CTLx pins controlled by SLP_Sx signals from Intel
®
chipset . . . . . . . . . . . 5
CTLx pins controlled by signals SUSPEND and AC_ADAPTER . . . . . . . . 7
3
Management of the EN pin to control the power consumption . . . . . . 8
3.1
3.2
EN tied to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EN driven by GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Management of the STCC50x1 attach detector . . . . . . . . . . . . . . . . . . . 9
4.1
4.2
EN and ATTACH_EN controlled by GPIOs . . . . . . . . . . . . . . . . . . . . . . . 10
ATTACH_EN = CTL3, CTLx pins controlled by SLP_Sx signals from
Intel chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
6
STCC50x1 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/14
DocID024781 Rev 1
AN4308
Management of CTLx pins to select operating mode
1
Management of CTLx pins to select operating mode
The selection between the SDP, CDP and DCP operating modes is done through a set of
control signals. The STCCxxxx devices have 3 logic inputs, the CTLx to select the suitable
operating mode in each platform power state (S0 to S5). The combination of these 3 pins
provides the following modes:
Table 1. CTLx truth table (assuming EN = 1, ATTACH_EN = 0)
Suitable
power state
CTL1 CTL2 CTL3
Mode
Advantages / use case
S0, S3
x
1
0
If NB is on battery and the battery charge is low,
it may be safer not to provide high current for
SDP with full remote wake- charging PD
(1)
.
up support
All PDs attached before transition from S0 to S3
are allowed to wake up the host to S0.
CDP
CDP with remote wake-up
support for low-speed PDs
DCP auto for full-speed
and high-speed PDs
Autodetect DCP mode
NB can supply high current to PD
Low-speed PDs attached before transition S0 to
S3 are allowed to wake up the host to S0.
Full-speed and high-speed devices are charged
in S3 state.
NB can charge PD with high current even if NB
is OFF (high power SMPS ON). The most
flexible, recommended charging mode.
NB can charge PD with high current even if NB
is OFF (high power SMPS ON). Standardized
USB charging mode enhanced to support also
Korean tablet PDs.
NB can charge PD with high current even if NB
is OFF (high power SMPS ON). Proprietary
charging mode for Apple PDs.
If NB battery is low, NB can stop charging
process using either this combination or EN pin.
S0
1
1
1
S3
0
1
1
S4/S5
0
0
1
S4/S5
1
0
0
Forced DCP BC1.2 mode
S4/S5
Any, but
mostly S4/S5
1
0
1
Forced DCP divider mode
0
0
0
OFF
1. PD stands for portable device, NB for notebook. LS stands for low-speed PDs, FS for full-speed PDs and HS for high-speed
PDs.
These pins may be controlled in different ways and depending on control types some
combinations are useless.
DocID024781 Rev 1
3/14
14
Management of CTLx pins to select operating mode
AN4308
Figure 1
shows the internal state diagram which manages these CTLx combinations.
Figure 1. Internal state diagram
4/14
DocID024781 Rev 1
AN4308
Application dependent CTLx controlling options
2
2.1
Application dependent CTLx controlling options
CTLx pins controlled by GPIO from embedded controller
In this case, full remote wakeup in the S3 can be achieved by not toggling CTL1 when the
NB enters the S3 state. Thus only 2 GPIOs are needed with the CTL1 and CTL2 tied
together. The CTL3 pin can be user-configurable (BIOS, etc.) to enable/disable the charging
feature.
Table 2. GPIO control truth table
Power state
S0/S3
S0/S3
(1)
S4/S5
Any, typically S4/S5
CTL1 = CTL2
1
1
0
0
CTL3
0
1
1
0
Mode
SDP
CDP
DCP auto
OFF
1. No charging of full-speed/high-speed PDs in the S3, but full remote wakeup support
2.2
CTLx pins controlled by SLP_Sx signals from Intel
®
chipset
New Intel chipset such as Chief River, X79 (Padsburg), NM10 (Pinetrail) have sleep signals
linked to NB power states, described as the SLP_Sx:
Table 3. SLP_Sx truth table
Power state
S0
S3
S4
S5
SLP_S3
1
0
0
0
SLP_S4
1
1
0
0
SLP_S5
1
1
1
0
DocID024781 Rev 1
5/14
14
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
