FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16507-2E
32
-
bit Proprietary Microcontroller
CMOS
FR60Lite
MB91260B Series
MB91263B/MB91264B/MB91F264B
■
DESCRIPTION
The MB91260B series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications
which require high-speed processing.
The CPU is used the FR family and the compatibility of FR60Lite.
■
FEATURES
•
FR60Lite CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method)
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
• Memory-to-memory transfer, bit handling, barrel shift instructions, etc. : Instructions suitable for embedded
applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
(Continued)
■
PACKAGES
100-pin plastic QFP
100-pin plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB91260B Series
(Continued)
• Register interlock function : Facilitates coding in assembler.
• Built-in multiplier with instruction-level support
•
32 bit multiplication with sign : 5 cycles
•
16 bit multiplication with sign : 3 cycles
• Interrupt (PC, PS save)
: 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• FR family instruction compatible
•
Internal peripheral functions
• Capacity of internal ROM and ROM type
MASK ROM : 128 Kbytes (MB91263B)/256 Kbytes (MB91264B)
FLASH ROM : 256 Kbytes (MB91F264B)
• Capacity of internal RAM : 8 Kbytes
• A/D converter (sequential comparison type)
• Resolution
: 10 bits : 2 channels
×
2 units, 8 channels
×
1 unit
• Conversion time : 1.2
µs
(Minimum conversion time system clock at 33 MHz)
1.35
µs
(Minimum conversion time system clock at 20 MHz)
• External interrupt input : 10 channels
• Bit search module (for REALOS)
Function for searching the MSB in each word for the first 1-to-0 inverted bit position
• UART (Full-duplex double buffer) : 3 channels
Selectable parity On/Off
Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
Internal timer for dedicated baud rate (U-Timer) on each channel
External clock can be used as transfer clock
Error detection function for parity, frame and overrun errors
• 8/16-bit PPG timer : 16 channels (at 8-bit) / 8 channels (at 16-bit)
• 16-bit reload timer : 3 channels (with cascade mode, without output of reload timer 0)
• 16-bit free-run timer : 1 channel
• 16-bit PWC timer : 2 channels
• Input capture : 4 channels (interface with free-run timer)
• Output compare : 6 channels (interface with free-run timer)
• Waveform generator
Various waveforms which are generated by using output compare, 16-bit PPG timer 0 and 16-bit dead timer
• MAC
RAM : instruction RAM
256
×
16-bit
XRAM
64
×
16-bit
YRAM
64
×
16-bit
Execution of 1 cycle product addition (16-bit
×
16-bit + 40 bits)
Operation results are extracted rounded from 40 to 16 bits
• DMAC (DMA Controller) : 5 channels
Operation of transfer and activation by internal peripheral interrupts and software
• Watchdog timer
• Low Power Consumption Mode
Sleep/stop function
•
Other
• Package : QFP-100, LQFP-100
• Technology : CMOS 0.35
µm
• Power supply : 1-power supply [Vcc
=
4.0 V to 5.5 V]
2
MB91260B Series
■
PIN ASSIGNMENT
(TOP VIEW)
P22/SCK0
P21/SOT0
P20/SIN0
P17
P16/PPG15
X0
X1
V
SS
V
CC
P15/PPG14
P14/PPG13
P13/PPG12
P12/PPG11
P11/PPG10
P10/PPG9
P07/PPG8
P06/PPG7
P05/PPG6
P04/PPG5
P03/PPG4
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P23/SIN1
P24/SOT1
P25/SCK1
P26/INT6
P27/INT7
P50
P51/TIN0
P52/TIN1
P53/TIN2
P54/INT0
P55/INT1
P56/INT2
P57/INT3
PG0/CKI/INT4
PG1/PPG0/INT5
PG2
V
CC
V
SS
C
PG3/SIN2
PG4/SOT2
PG5/SCK2
P40
P41
P42
P43
P44
P45
P46
P47
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P02/PPG3
P01/PPG2
P00/PPG1
INIT
MD0
MD1
MD2
NMI
P77/ADTG2
P76/ADTG1
P75/ADTG0
P74/PWI1
V
SS
V
CC
P73/PWI0
P72/DTTI
P71/TOT2
P70/TOT1
P63/INT9
P62/INT8
P61/IC3
P60/IC2
P37/IC1
P36/IC0
P35/RTO5
P34/RTO4
P33/RTO3
P32/RTO2
P31/RTO1
P30/RTO0
PE1/AN11
PE0/AN10
AVRH2
ACC
AV
CC
AVRH1
AV
SS
PD1/AN9
PD0/AN8
AVRH0
PC7/AN7
PC6/AN6
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
V
CC
V
SS
(FPT-100-M06)
(Continued)
3
MB91260B Series
(Continued)
(TOP VIEW)
P25/SCK1
P26/INT6
P27/INT7
P50
P51/TIN0
P52/TIN1
P53/TIN2
P54/INT0
P55/INT1
P56/INT2
P57/INT3
PG0/CKI/INT4
PG1/PPG0/INT5
PG2
V
CC
V
SS
C
PG3/SIN2
PG4/SOT2
PG5/SCK2
P40
P41
P42
P43
P44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P24/SOT1
P23/SIN1
P22/SCK0
P21/SOT0
P20/SIN0
P17
P16/PPG15
X0
X1
V
SS
V
CC
P15/PPG14
P14/PPG13
P13/PPG12
P12/PPG11
P11/PPG10
P10/PPG9
P07/PPG8
P06/PPG7
P05/PPG6
P04/PPG5
P03/PPG4
P02/PPG3
P01/PPG2
P00/PPG1
INIT
MD0
MD1
MD2
NMI
P77/ADTG2
P76/ADTG1
P75/ADTG0
P74/PWI1
V
SS
V
CC
P73/PWI0
P72/DTTI
P71/TOT2
P70/TOT1
P63/INT9
P62/INT8
P61/IC3
P60/IC2
P37/IC1
P36/IC0
P35/RTO5
P34/RTO4
P33/RTO3
P32/RTO2
4
P45
P46
P47
PE1/AN11
PE0/AN10
AVRH2
ACC
AV
CC
AVRH1
AV
SS
PD1/AN9
PD0/AN8
AVRH0
PC7/AN7
PC6/AN6
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
V
CC
V
SS
P30/RTO0
P31/RTO1
(FPT-100-M05)
MB91260B Series
■
PIN DESCRIPTION
Pin no.
QFP
LQFP
Pin name
Circuit
type
Description
UART1 data input pin. Since this input is used as required when UART1 is
performing input operation, the port output must remain off unless used in-
tentionally.
General-purpose I/O port. This port is enabled when UART1 data input is
disabled.
UART1 data output pin. This function is enabled when UART1 data output
is enabled.
General-purpose I/O port. This function is enabled when UART1 data out-
put is disabled.
UART1 clock input/output pin. This function is enabled when UART1 clock
output is enabled.
General-purpose I/O port. This function is enabled when UART1 clock out-
put is disabled.
External interrupt input pin. Since this input is used as required when the
corresponding external interrupt is enabled, the port output must remain off
unless used intentionally.
General-purpose I/O port. This function is enabled when external interrupt
input is disabled.
External interrupt input pin. Since this input is used as required when the
corresponding external interrupt is enabled, the port output must remain off
unless used intentionally.
General-purpose I/O port. This function is enabled when external interrupt
input is disabled.
C
General-purpose I/O port. This port is enabled in single-chip mode.
Reload timer 0 external trigger input pin. Since this input is used as re-
quired when trigger input is enabled, the port output must remain off unless
used intentionally.
General-purpose I/O port. This function is enabled when reload timer 0 ex-
ternal clock input is disabled.
Reload timer 1 external trigger input pin. Since this input is used as re-
quired when trigger input is enabled, the port output must remain off unless
used intentionally.
General-purpose I/O port. This function is enabled when reload timer 1 ex-
ternal clock input is disabled.
Reload timer 2 external trigger input pin. Since this input is used as re-
quired when trigger input is enabled, the port output must remain off unless
used intentionally.
General-purpose I/O port. This function is enabled when reload timer 2 ex-
ternal clock input is disabled.
(Continued)
SIN1
1
99
P23
SOT1
2
100
P24
SCK1
3
1
P25
D
D
D
INT6
4
2
P26
E
INT7
5
3
P27
6
4
P50
TIN0
7
5
P51
C
E
TIN1
8
6
P52
C
TIN2
9
7
P53
C
5
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