AN4655
Application note
Virtually increasing the number of serial communication peripherals
in STM32 applications
Introduction
Application engineers often face the problem of limited number of serial communication
peripherals of a microcontroller that, on the other hand fulfills all the other application
requirements thanks to its features and performance. Sometimes they obviate by switching
to a higher level microcontroller with sufficient number of communication peripherals. This
migration brings with it additional (often unused) performance and functionality, in most
cases unneeded and not used by application, in addition to increased costs and PCB
complexity.
A frequent case is when full (or specific) functionality is not required for each and every
channel, in this case the communication flow and its control can be simplified radically (e.g.
communication is required at specific modes or time slots only, communication speed can
be lower, correct timing is not strictly required for all the signals, simplified protocol or flow is
acceptable). In these specific cases the user would really benefit from methods on how to
supplement the missing channel(s) with current HW, to avoid needless migrations.
On the other side, reaching nearly full compatibility with all the native HW features is hardly
achievable at an alternate channel, besides costing a lot in terms of code and performance.
Usually it is preferable to abandon some specific requirements with the goal of simplify the
concept of the alternated peripheral channel. A crucial point here is to recognize those
undemanding channels in the application, which can be altered with lower effort and loss of
performance.
This application note provides a basic overview of the described issue, and will help the
application engineers to identify possible alternate methods when implementing missing
communication channels. It applies to all STM32 microcontrollers, as the discussed
peripherals are present on all products of this class.
Additional informations and examples can be found in the following reference documents,
describing actual cases and solutions:
•
TN0072, Software toolchains and STM32 features;
•
UM0892, STM32 ST-LINK Utility software description;
•
AN4457, STM32F4 full Duplex UART emulation.
The last cited document is being developed together with other application notes on the
same topic, user should check their availability on
www.st.com.
March 2015
DocID027483 Rev 1
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Contents
AN4655
Contents
1
2
HW methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SW methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Compatibility factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1
2.1.2
2.1.3
2.1.4
Functionality (not related to timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
HW Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
API interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bit banging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Combination of HW and SW control of GPIOs . . . . . . . . . . . . . . . . . . . . 9
Master vs. slave, clock signal aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interrupts and DMA vs. bit-banging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
UART duplex channel based on combination of HW and SW control
of GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI bit-banging sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2C master bit-banging sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2
Applicable methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1
2.2.2
2.3
Common principles of the methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1
2.3.2
2.4
Peripherals specific aspects of SW emulation . . . . . . . . . . . . . . . . . . . . . .11
2.4.1
2.4.2
2.4.3
2.5
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1
2.5.2
2.5.3
3
4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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List of tables
List of tables
Table 1.
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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List of figures
AN4655
List of figures
Figure 1.
Figure 2.
Figure 3.
Remapping option principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Multiplexing principle while using dedicated group of routing interface (RI) . . . . . . . . . . . . . 6
UART duplex channel based on timer capture events . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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HW methods
1
HW methods
If addition of native HW peripherals is not acceptable (e.g. by adding external components
like a dedicated communication coprocessor unit), then the limited number of peripherals
can be compensated by the following basic methods:
1.
Use internal remapping option of dedicated peripheral instances, to change the inputs
and outputs available at different ports, thus establishing a temporary connection of the
microcontroller with a different channel (the user can find informations about alternate
function capability in the pin-out description of datasheets, for each product and its
implemented peripherals).
Multiplexing communication channels into a single communication port while using
multiplexing logic.
Using SWO feature.
2.
3.
The first two methods provide service on selected channel exclusively in dedicated time
slots, and can be used only when contemporary operation and permanent monitoring of
altered channels is not strictly required, as it happens, for example, in:
•
•
•
•
service channels;
occasional communication with remote devices;
monitoring of sensors with slow data value change;
channels used for periodical backup.
These methods are suitable for master communications when any slave activity is expected
upon master request, or when some communication with slave can be missed and can be
easily back re-synchronized when master reconnects back to the channel to be serviced
(listened and talked to). It could be used at slave side, too, when some additional control
signals are provided between slave and master to inform the slave that connection is
established (e.g. chip select or channel ready/busy signalizing when slave can/can’t operate
with the channel).
Anyway, user should take care about inactive state at GPIOs associated with a peripheral
instance bus signals when alternate function is remapped or multiplexed to another channel.
A proper setting ensures emulation of idle condition and prevents any stuck at channels not
currently selected or just not used for communication. This can be achieved with a correct
configuration of GPIO port registers, and partially by adding external components (pull
up/pull down resistors). Note that GPIO logic commonly overtakes control over the
associated pins when alternate functionality is removed (remapped) from the port and user
has to prevent any bus false state detection on such temporarily frozen channels.
For multiplexing, user can use specific control of I/O switches at dedicated groups of routing
interface if it is available for the product. User must ensure that a proper combination (pair)
of switches within a single group be closed in time to let the signal pass through the desired
path. User has to dedicate additional IOs for such switching, so they are lost for other
purposes, and there is additional PCB routing.
The principle is shown in
Figure 1
and
Figure 2.
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