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47
CY29947
2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer
Features
•
•
•
•
•
•
•
•
•
•
2.5V or 3.3V operation
200-MHz clock support
LVCMOS-/LVTTL-compatible inputs
9 clock outputs: drive up to 18 clock lines
Synchronous Output Enable
Output three-state control
250 ps max. output-to-output skew
Pin compatible with MPC947, MPC9447
Available in Industrial and Commercial temp. range
32-pin TQFP package
Description
The CY29947 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select one of two LVCMOS/LVTTL
compatible clock inputs. The two clock sources can be used
to provide for a test clock as well as the primary system clock.
All other control inputs are LVCMOS/LVTTL compatible. The 9
outputs are LVCMOS or LVTTL compatible and can drive 50Ω
series or parallel terminated transmission lines.For series ter-
minated transmission lines, each output can drive one or two
traces giving the device an effective fanout of 1:18. The out-
puts can also be three-stated via the three-state input TS#.
Low output-to-output skews make the CY29947 an ideal clock
distribution buffer for nested clock trees in the most demand-
ing of synchronous systems.
The CY29947 also provides a synchronous output enable in-
put for enabling or disabling the output clocks. Since this input
is internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
Pin Configuration
VDDC
VDDC
27
VSS
VSS
VSS
25
24
23
22
21
20
19
18
17
Q0
Q1
28
Q2
26
VDD
TCLK0
TCLK1
TCLK_SEL
SYNC_OE
TS#
0
1
VDDC
32
31
30
VSS
TCLK_SEL
TCLK0
TCLK1
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
29
VSS
Q3
VDDC
Q4
VSS
Q5
VDDC
VSS
9
Q0-Q8
CY29947
10
11
12
13
14
VDDC
15
Q6
16
VSS
9
VSS
VSS
Q8
Cypress Semiconductor Corporation
Document #: 38-07287 Rev. *C
•
3901 North First Street
•
San Jose
VDDC
•
CA 95134 • 408-943-2600
Revised December 22, 2002
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Q7
CY29947
Pin Description
[1]
Pin
3
4
2
11, 13, 15, 19,
21, 23, 26, 28,
30
5
6
10, 14, 18, 22,
27, 31
7
1, 8, 9, 12, 16,
17, 20, 24, 25,
29, 32
Name
TCLK0
TCLK1
TCLK_SEL
Q(8:0)
VDDC
PWR
I/O
I, PU
I, PU
I, PU
O
Test Clock Input
Test Clock Input
Test Clock Select Input.
When LOW, TCLK0 is selected. When assert-
ed HIGH, TCLK1 is selected.
Clock Outputs
Description
SYNC_OE
TS#
VDDC
VDD
VSS
I, PU
I, PU
Output Enable Input.
When asserted HIGH, the outputs are enabled
and when set LOW the outputs are disabled in a LOW state.
Three-state Control Input.
When asserted LOW, the output buffers are
three-stated. When set HIGH, the output buffers are enabled.
3.3V or 2.5V Power Supply for Output Clock Buffers
3.3V or 2.5V Power Supply
Common Ground
Note:
1. PD = internal pull-down, PU = internal pull-up.
Output Enable/Disable
The CY29947 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are dis-
abled in a LOW state. When SYNC_OE is set HIGH, the out-
puts are enabled as shown in
Figure 1.
TCLK
SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
Document #: 38-07287 Rev. *C
Page 2 of 7
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CY29947
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
: ............. V
SS
– 0.3V
Maximum Input Voltage Relative to V
DD
:............. V
DD
+ 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum ESD protection ................................................ 2kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
or V
DD
).
DC Parameters:
V
DD
= V
DDC
= 3.3V ±10% or 2.5V ±5%, Over the specified temperature range
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DDQ
I
DD
Description
Input Low Voltage
Input High Voltage
Input Low Current
[3]
Input High Current
[3]
Output Low Voltage
[4]
Output High Voltage
[4]
Quiescent Supply
Current
Dynamic Supply
Current
V
DD
= 3.3V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 3.3V, Outputs @ 160 MHz,
CL = 30 pF
V
DD
= 2.5V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 2.5V, Outputs @ 160 MHz,
CL = 30 pF
Zout
C
in
Output Impedance
Input Capacitance
V
DD
= 3.3V
V
DD
= 2.5V
12
14
I
OL
= 20 mA
I
OH
= –20 mA, V
DD
= 3.3V
I
OH
= –20 mA, V
DD
= 2.5V
2.5
1.8
5
120
200
85
140
15
18
4
18
22
pF
Ω
7
mA
mA
Conditions
Min.
V
SS
2.0
Typ.
Max.
0.8
V
DD
–100
10
0.4
Unit
V
V
µA
µA
V
V
Notes:
2.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50Ω (or 50Ω to V
DD
/2) transmission lines.
Document #: 38-07287 Rev. *C
Page 3 of 7
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CY29947
AC Parameters
[5]
:
V
DD
= V
DDC
= 3.3V ±10% or 2.5V ±5%, Over the specified temperature range
Parameter
Fmax
Tpd
FoutDC
tpZL, tpZH
tpLZ, tpHZ
Tskew
Tskew(pp)
Ts
Th
Tr/Tf
Description
Input Frequency
[6]
TCLK To Q Delay
[6]
Output Duty Cycle
[6, 7]
Output Enable Time (all outputs)
Output Disable Time (all outputs)
Output-to-Output Skew
[6, 8]
Part-to-Part Skew
[9]
Set-up Time
[6, 10]
Hold Time
[6, 10]
Output Clocks Rise/Fall Time
[8]
SYNC_OE to TCLK
TCLK to SYNC_OE
0.8V to 2.0V,
V
DD
= 3.3V
0.6V to 1.8V,
V
DD
= 2.5V
0.0
1.0
0.20
0.20
1.0
1.3
Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
Measured at V
DD
/2
4.75
6.50
45
2
2
150
Min.
Typ.
Max.
200
170
9.25
10.50
55
10
10
250
2.0
%
ns
ns
ps
ns
ps
ps
ns
ns
Unit
MHz
Notes:
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50Ω transmission lines.
7. 50% input duty cycle.
8. See
Figure 2.
9. Part-to-Part skew at a given temperature and voltage.
10. Set-up and hold times are relative to the falling edge of the input clock
Document #: 38-07287 Rev. *C
Page 4 of 7
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