TS68020
HCMOS 32-bit Virtual Memory Microprocessor
Datasheet
Features
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Object Code Compatible with Earlier TS68000 Microprocessors
Addressing Mode Extensions for Enhanced Support of High Level Languages
New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics
Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth
Co-processor Interface to Companion 32-bit Peripherals: TS68881 and TS68882 Floating Point Co-processors
Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions to be Executed Concurrently
High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits
Dynamic Bus Sizing Efficiently Supports 8-, 16-, 32-bit Memories and Peripherals
Full Support of Virtual Memory and Virtual Machine
Sixteen 32-bit General-purpose Data and Address Registers
Two 32-bit Supervisor Stack Pointers and 5 Special Purpose Control Registers
18 Addressing Modes and 7 Data Types
4-Gbyte Direct Addressing Range
Processor Speed: 16.67 MHz – 20 MHz – 25 MHz – 33.33 MHz
Power Supply: 5.0 V
DC
± 10%
Description
The TS68020 is the first full 32-bit implementation of the TS68000 family of microprocessors. Using HCMOS technology,
the TS68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile
addressing modes.
Screening/Quality
This product is manufactured in full compliance with either:
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MIL-STD-883 (class B)
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DESC 5962 - 860320
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or according to e2v standards
See
“Ordering Information” on page 45.
Pin connection: see
page 4.
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2015
1101B–HIREL–02/15
TS68020
R suffix
PGA 114
Ceramic Pin Grid Array
F suffix
CQFP 132
Ceramic Quad Flat Pack
A suffix
CERQUAD 132
(Ceramic Quad Flat Pack)
1. Introduction
The TS68020 is a high-performance 32-bit microprocessor. It is the first microprocessor to have evolved
from a 16-bit machine to a full 32-bit machine that provides 32-bit address and data buses as well as 32-
bit internal structures. Many techniques were utilized to improve performance and at the same time
maintain compatibility with other processors of the TS68000 Family. Among the improvements are new
addressing modes which better support high-level language structures, an expanded instruction set
which provides 32-bit operations for the limited cases not supported by the TS68000 and several new
instructions which support new data types. For special-purpose applications when a general-purpose
processor alone is not adequate, a co-processor interface is provided.
The TS68020 is a high-performance microprocessor implemented in HCMOS, low power, small
geometry process. This process allows CMOS and HMOS (high density NMOS) gates to be combined
on the same device. CMOS structures are used where speed and low power is required, and HMOS
structures are used where minimum silicon area is desired. This technology enables the TS68020 to be
very fast while consuming less power (less than 1.5 watts) and still have a reasonably small die size. It
utilizes about 190.000 transistors, 103.000 of which are actually implemented. The package is a pin-grid
array (PGA) with 114 pins, arranged 13 pins on a side with a depopulated center and 132 pins ceramic
quad flat pack (CQFP and CERQUAD).
Figure 1-1
is a block diagram of the TS68020. The processor can be divided into two main sections: the
bus controller and the micromachine. This division reflects the autonomy with which the sections
operate.
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TS68020
Figure 1-1.
TS68020 Block Diagram
The bus controller consists of the address and data pads and multiplexers required to support dynamic
bus sizing, a macro bus controller which schedules the bus cycles on the basis of priority with two state
machines (one to control the bus cycles for operated accesses and the other to control the bus cycles for
instruction accesses), and the instruction cache with its associated control.
The micromachine consists of an execution unit, nanorom and microrom storage, an instruction decoder,
an instruction pipe, and associated control sections. The execution unit consists of an address section,
an operand address section, and a data section. Microcode control is provided by a modified two-level
store of microrom and nanorom. Programmed logical arrays (PLAs) are used to provide instruction
decode and sequencing information. The instruction pipe and other individual control sections provide
the secondary decode of instructions and generated the actual control signals that result in the decoding
and interpretation of nanorom and micorom information.
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TS68020
Figure 1-2.
PGA Terminal Designation - R Suffix
Figure 1-3.
CQFP Terminal Designation - F Suffix
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TS68020
Figure 1-4.
CERQUAD Terminal Designation - A Suffix
NC*
NC*
GND
BG
V
CC
GND
GND
CLK
RESET
V
CC
V
CC
RMC
FC0
FC1
FC2
SIZ0
SIZ1
DBEN
ECS
CDIS
AVEC
DSACK0
DSACK1
BERR
GND
GND
HALT
AS
DS
GND
GND
R/W
NC*
NC*
BGACK
BR
A0
A1
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
V
CC
V
CC
GND
GND
A16
A15
A14
A13
A12
A11
A10
NC*
NC*
17
1
117
68020
CERQUAD132
(window frame down)
Top VIEW
50
NC*
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
GND
GND
V
CC
V
CC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
NC*
NC*
83
*NC = Do not connect to this pin.
NC*
NC*
NC*
A9
A8
A7
A6
A5
A4
A3
A2
GND
OCS
IPEND
V
CC
V
CC
GND
GND
IPL2
IPL1
IPL0
D0
D1
D2
D3
D4
GND
GND
V
CC
V
CC
D5
NC*
NC*
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1101B–HIREL–02/15
e2v semiconductors SAS 2015
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