PD-95210
IRF7807VPbF
•
•
•
•
N Channel Application Specific MOSFET
Ideal for Mobile DC-DC Converters
Low Conduction Losses
Low Switching Losses
100% R
G
Tested
Lead-Free
HEXFET
®
Power MOSFET
S
S
S
1
2
3
4
8
7
A
D
D
D
D
6
5
Description
This new device employs advanced HEXFET Power
MOSFET technology to achieve an unprecedented
balance of on-resistance and gate charge. The
reduction of conduction and switching losses makes
it ideal for high efficiency DC-DC Converters that
power the latest generation of mobile microprocessors.
A pair of IRF7807V devices provides the best cost/
performance solution for system voltages, such as
3.3V and 5V.
G
SO-8
T o p V ie w
DEVICE CHARACTERISTICS
R
DS(on)
Q
G
Q
SW
Q
OSS
IRF7807V
17 mΩ
9.5 nC
3.4 nC
12 nC
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain or Source
T
A
= 25°C
T
A
= 70°C
T
A
= 25°C
T
A
= 70°C
(V
GS
≥
4.5V)
Symbol
V
DS
V
GS
I
D
I
DM
P
D
T
J
, T
STG
I
S
I
SM
IRF7807V
30
±20
8.3
6.6
66
2.5
1.6
-55 to 150
2.5
66
Units
V
Power Dissipation
eÃÃÃÃÃÃÃ
Pulsed Drain Current
Pulsed Source Current
A
W
°C
A
Junction & Storage Temperature Range
Continuous Source Current (Body Diode)
Thermal Resistance
Parameter
Maximum Junction-to-Ambient
Maximum Junction-to-Lead
h
eh
Symbol
R
θJA
R
θJL
Typ
–––
–––
Max
50
20
Units
°C/W
11/3/04
IRF7807VPbF
Electrical Characteristics
Parameter
Drain-Source Breakdown Voltage
Static Drain-Source On-Resistance
Gate Threshold Voltage
Drain-Source Leakage Current
Gate-Source Leakage Current*
Total Gate Charge*
Pre-Vth Gate-Source Charge
Post-Vth Gate-Source Charge
Gate-to-Drain Charge
Switch Charge (Q
gs2
+ Q
gd
)
Output Charge*
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Symbol
BV
DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Q
G
Q
GS1
Q
GS2
Q
GD
Q
SW
Q
OSS
R
G
t
d(on)
t
r
t
d(off)
t
f
Min Typ Max Units
30
–––
1.0
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.9
–––
–––
–––
–––
–––
17
–––
–––
–––
–––
9.5
2.3
1.0
2.4
3.4
12
–––
6.3
1.2
11
2.2
–––
25
3.0
100
20
100
nA
14
–––
–––
–––
5.2
16.8
2.8
–––
–––
–––
–––
ns
Ω
V
DD
= 16V
I
D
= 7A
nC
µA
V
mΩ
V
Conditions
V
GS
= 0V, I
D
= 250µA
V
GS
= 4.5V, I
D
= 7.0A
V
DS
= 30V, V
GS
= 0
V
DS
= 24V, V
GS
= 0
V
DS
= 24V, V
GS
= 0, T
J
= 100°C
V
GS
= ± 20V
V
GS
= 5V, I
D
= 7.0A
V
DS
= 16V
d
V
DS
= V
GS
, I
D
= 250µA
––– ±100
V
DS
= 16V, V
GS
= 0
V
GS
= 5V, R
G
= 2Ω
Resistive Load
Source-Drain Ratings and Characteristics
Parameter
Diode Forward Voltage*
Reverse Recovery Charge
Reverse Recovery Charge
(with Parallel Schottsky)
Symbol
V
SD
Q
rr
Q
rr(s)
Min Typ Max Units
–––
–––
–––
–––
64
41
1.2
–––
nC
–––
V
I
S
= 7.0A
d
,V
Conditions
GS
= 0V
f
di/dt = 700A/µs
V
DS
= 16V, V
GS
= 0V, I
S
= 7.0A
di/dt = 700A/µs , (with 10BQ040)
V
DS
= 16V, V
GS
= 0V, I
S
= 7.0A
f
Notes:
*
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width
≤
400 µs; duty cycle
≤
2%.
When mounted on 1 inch square copper board
Typ = measured - Q
oss
Typical values of R
DS
(on) measured at V
GS
= 4.5V, Q
G
, Q
SW
and Q
OSS
measured at V
GS
= 5.0V, I
F
= 7.0A.
R
θ
is measured at T
J
approximately 90°C
Device are 100% tested to these parameters.
2
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IRF7807VPbF
Power MOSFET Selection for DC/DC
Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on)
of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Drain Current
4
1
Gate Voltage
t2
V
GTH
t0
t1
t3
Q
GS1
Q
GS2
2
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
P
loss
=
(
I
rms
×
R
ds(on )
)
2
Figure 1: Typical MOSFET switching waveform
⎛
Q
⎜
I
×
gd
×
V
in
×
+
i
g
⎝
+
(
Q
g
×
V
g
×
f
)
+
⎛
Q
oss
×
V
in
×
f
⎞
⎝
2
⎠
Q
gs 2
⎞ ⎛
⎞
f
⎟ + ⎜
I
×
×
V
in
×
f
⎟
i
g
⎠ ⎝
⎠
Synchronous FET
The power loss equation for Q2 is approximated
by;
*
P
loss
=
P
conduction
+
P
+
P
output
drive
P
loss
=
I
rms
×
R
ds(on)
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 1.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached (t1) and the time the drain
current rises to I
dmax
(t2) at which time the drain volt-
age begins to change. Minimizing Q
gs2
is a critical fac-
tor in reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure 2 shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
+
(
g
×
V
g
×
f
)
Q
(
Q
GD
Drain Voltage
2
)
⎛
Q
⎞
+ ⎜
oss
×
V
in
×
f
+
(
Q
rr
×
V
in
×
f
)
⎝
2
⎠
*dissipated primarily in Q1.
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3
IRF7807VPbF
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
Typical Mobile PC Application
The performance of these new devices has been tested
in circuit and correlates well with performance predic-
tions generated by the system models. An advantage of
this new technology platform is that the MOSFETs it
produces are suitable for both control FET and synchro-
nous FET applications. This has been demonstrated with
the 3.3V and 5V converters. (Fig 3 and Fig 4). In these
applications the same MOSFET IRF7807V was used for
both the control FET (Q1) and the synchronous FET
(Q2). This provides a highly effective cost/performance
solution.
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Spice model for IRF7807V can be downloaded in
machine readable format at www.irf.com.
Figure 2: Q
oss
Characteristic
3.3V Supply : Q1=Q2= IRF7807V
93
92
91
Efficiency (%)
89
88
87
86
85
84
83
1
2
3
Load current (A)
4
5
Vin=24V
Vin=14V
Vin=10V
5.0V Supply : Q1=Q2= IRF7807V
95
94
93
Efficiency (%)
92
91
90
89
88
87
86
1
2
3
Load current (A)
4
5
Vin=24V
Vin=14V
Vin=10V
90
4
Figure 3
Figure 4
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IRF7807VPbF
2.0
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
= 7.0A
5
I
D
=
7.0A
V
DS
= 16V
V
GS
, Gate-to-Source Voltage (V)
V
GS
= 4.5V
0
20
40
60
80 100 120 140 160
1.5
4
3
1.0
2
0.5
1
0.0
-60 -40 -20
0
T
J
, Junction Temperature (
°
C)
0
2
4
6
8
10
12
Q
G
, Total Gate Charge (nC)
Fig 5.
Normalized On-Resistance
Vs. Temperature
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
RDS(on) , Drain-to -Source On Resistance (Ω )
0.030
100
I
SD
, Reverse Drain Current (A)
0.025
T
J
= 150
°
C
10
0.020
ID = 7.0A
0.015
T
J
= 25
°
C
1
0.010
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
0.1
0.2
V
GS
= 0 V
0.4
0.6
0.8
1.0
1.2
VGS, Gate -to -Source Voltage (V)
V
SD
,Source-to-Drain Voltage (V)
Fig 7.
On-Resistance Vs. Gate Voltage
Fig 8.
Typical Source-Drain Diode
Forward Voltage
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5
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