IRF7807TRPbF-1
IRF7807ATRPbF-1
HEXFET
®
Chip-Set for DC-DC Converters
V
DS
R
DS(on) max
(@V
GS
= 4.5V)
30
25
12
8.3
V
mΩ
nC
A
S
S
S
G
1
2
3
4
8
7
A
D
D
D
D
6
5
Q
g (typical)
I
D
(@T
A
= 25°C)
T o p V ie w
SO-8
Features
Benefits
Industry-standard pinout SO-8 Package
Compatible with Existing Surface Mount Techniques
RoHS Compliant, Halogen-Free
MSL1, Industrial qualification
⇒
Multi-Vendor Compatibility
Easier Manufacturing
Environmentally Friendlier
Increased Reliability
Base Part Number
IRF7807PbF-1
IRF7807APbF-1
Package Type
SO-8
Standard Pack
Form
Quantity
Tape and Reel
4000
Tape and Reel
4000
Orderable Part Number
IRF7807TRPbF-1
IRF7807ATRPbF-1
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain or Source
Current (V
GS
≥
4.5V)
Pulsed Drain Current
Power Dissipation
25°C
70°C
Junction & Storage Temperature Range
Continuous Source Current (Body Diode)
Pulsed source Current
Thermal Resistance
Parameter
Maximum Junction-to-Ambient
1
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2014 International Rectifier
Symbol
V
DS
V
GS
25°C
70°C
I
DM
P
D
T
J
, T
STG
I
S
I
SM
I
D
IRF7807
30
±12
8.3
6.6
66
2.5
1.6
IRF7807A
Units
V
8.3
6.6
66
A
W
°C
2.5
66
A
–55 to 150
2.5
66
R
θJA
Max.
50
Units
°C/W
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IRF7807/ATRPbF-1
Electrical Characteristics
Parameter
Drain-to-Source
Breakdown Voltage*
Static Drain-Source
on Resistance*
Gate Threshold Voltage*
Drain-Source Leakage
Current*
V
(BR)DSS
R
DS
(on)
V
GS
(th)
I
DSS
1.0
30
150
I
GSS
Q
g
Q
gs1
Q
gs2
Q
gd
Q
SW
Q
oss
R
g
t
d
(on)
t
r
t
d
(off)
t
f
12
2.1
0.76
2.9
3.66
14
1.2
12
17
25
6
5.2
16.8
±100
17
12
2.1
0.76
2.9
3.66
14
1.2
12
17
25
6
ns
16.8
Ω
V
DD
= 16V
I
D
= 7A
R
g
= 2Ω
V
GS
= 4.5V
Resistive Load
Conditions
I
S
= 7A, V
GS
= 0V
di/dt = 700A/μs
V
DS
= 16V, V
GS
= 0V, I
S
= 7A
di/dt = 700A/μs
(with 10BQ040)
V
DS
= 16V, V
GS
= 0V, I
S
= 7A
V
DS
= 16V, V
GS
= 0
nC
IRF7807
Min Typ Max
30
–
17
–
25
IRF7807A
Min Typ Max Units
30
–
17
1.0
30
150
±100
17
nA
–
25
V
mΩ
V
μA
Conditions
V
GS
= 0V, I
D
= 250μA
V
GS
= 4.5V, I
D
= 7A
V
DS
= V
GS
, I
D
= 250μA
V
DS
= 24V, V
GS
= 0
V
DS
= 24V, V
GS
= 0,
Tj = 100°C
V
GS
= ±12V
V
GS
= 5V, I
D
= 7A
V
DS
= 16V, I
D
= 7A
Gate-Source Leakage
Current*
Total Gate Charge*
Pre-Vth
Gate-Source Charge
Post-Vth
Gate-Source Charge
Gate to Drain Charge
Switch Charge*
(Q
gs2
+ Q
gd
)
Output Charge*
Gate Resistance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Source-Drain Rating & Characteristics
Parameter
Diode Forward
Voltage*
Reverse Recovery
Charge
Reverse Recovery
Charge (with Parallel
Schotkky)
Notes:
*
Min
V
SD
Q
rr
Q
rr(s)
Typ Max
1.2
80
50
Min
Typ Max Units
1.2
80
50
V
nC
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width
≤
300
μs;
duty cycle
≤
2%.
When mounted on 1 inch square copper board, t < 10 sec.
Typ = measured - Q
oss
Devices are 100% tested to these parameters.
2
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IRF7807/ATRPbF-1
Power MOSFET Selection for DC/DC
Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called the
Control FET, are impacted by the R
ds(on)
of the MOSFET,
but these conduction losses are only about one half of
the total losses.
Power losses in the control switch Q1 are given by;
Drain Current
4
1
Gate Voltage
t2
V
GTH
t0
t1
t3
Q
GS1
This can be expanded and approximated by;
Figure 1: Typical MOSFET switching waveform
P
loss
=
(
I
rms 2
×
R
ds(on )
)
⎛
Q
gs2
Q
gd
⎞ ⎛
⎞
+⎜
I
×
×
V
in
×
f
⎟ + ⎜
I
×
×
V
in
×
f
⎟
i
g
i
g
⎝
⎠ ⎝
⎠
+
(
Q
g
×
V
g
×
f
)
+
⎛
Q
oss
×
V
in
×
f
⎞
⎝
2
⎠
Synchronous FET
The power loss equation for Q2 is approximated
by;
*
P
loss
=
P
conduction
+
P
drive
+
P
output
P
loss
=
I
rms
×
R
ds(on)
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source charge
that is included in all MOSFET data sheets. The impor-
tance of splitting this gate-source charge into two sub
elements, Q
gs1
and Q
gs2
, can be seen from Fig 1.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold volt-
age has been reached (t1) and the time the drain cur-
rent rises to I
dmax
(t2) at which time the drain voltage
begins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the output
capacitance of the MOSFET during every switching
cycle. Figure 2 shows how Q
oss
is formed by the paral-
lel combination of the voltage dependant (non-linear)
capacitance’s C
ds
and C
dg
when multiplied by the power
supply input buss voltage.
+
(
Q
g
×
V
g
×
f
)
(
Q
GD
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
Q
GS2
2
Drain Voltage
2
)
⎛
Q
⎞
Q
+ ⎜
oss
×
V
in
×
f
+
(
rr
×
V
in
×
f
)
⎝
2
⎠
*dissipated primarily in Q1.
3
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IRF7807/ATRPbF-1
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the impor-
tance of gate charge must not be overlooked since it
impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
Typical Mobile PC Application
The performance of these new devices has been tested
in circuit and correlates well with performance predic-
tions generated by the system models. An advantage
of this new technology platform is that the MOSFETs
it produces are suitable for both control FET and syn-
chronous FET applications. This has been demon-
strated with the 3.3V and 5V converters. (Fig 3 and
Fig 4). In these applications the same MOSFET IRF7807
was used for both the control FET (Q1) and the syn-
chronous FET (Q2). This provides a highly effective
cost/performance solution.
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Spice model for IRF7807 can be downloaded in ma-
chine readable format at www.irf.com.
Figure 2: Q
oss
Characteristic
3.3V Supply : Q1=Q2=IRF7807
93
92
91
Efficiency (%)
Efficiency (%)
94
93
92
91
95
5V Supply : Q1=Q2=IRF7807
90
89
88
87
86
85
84
1
1.5
2
2.5
3
3.5
Load Current (A)
4
4.5
5
Vin = 10V
Vin = 14V
Vin = 24V
Vin = 10V
90
89
1
1.5
Vin = 14V
Vin=24V
2
2.5
3
3.5
Load Current (A)
4
4.5
5
Figure 3
4
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Figure 4
October 16, 2014
IRF7807/ATRPbF-1
Typical Characteristics
IRF7807
IRF7807A
Figure 5. Normalized On-Resistance vs. Temperature
Figure 6. Normalized On-Resistance vs. Temperature
Figure 7. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 8. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 9. Typical Rds(on) vs. Gate-to-Source Voltage
5
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Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage
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October 16, 2014
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