AN95089
PSoC
®
4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
Author: Prakhar Agarwal
Associated Part Family: CY8C4XX7-BL, CY8C4xx8-BL, CYBL10X6X, CYBL10x7x
Related Application Notes: None
AN95089 provides insights into the selection and tuning of the external crystal oscillator (ECO) and watch crystal oscillator
(WCO) for PSoC 4/ PRoC BLE devices to achieve a good RF performance. This application note introduces basics of
crystals and clock accuracy measurements. Cypress-recommended crystals and tuning techniques for optimum
performance are also discussed.
Contents
1
2
Introduction ...............................................................1
Crystal Oscillator Basics ...........................................2
2.1
Crystal Oscillator Circuitry................................ 2
2.2
Load Cap Value (C
L
) ........................................2
2.3
Crystal Equivalent RLC Circuit.........................4
2.4
Drive Level .......................................................5
2.5
PPM Error ........................................................5
Effects of Inaccurate ECO Crystal Frequency
on RF Performance ..................................................5
Crystal Tuning Technique for ECO ...........................6
4.1
Steps to Correct Clock Inaccuracy ...................7
Is Tuning Required for Each Board? ........................8
Crystal Analysis for ECO ........................................ 10
6.1
Frequency Variation with Temperature .......... 10
6.2
Frequency Variation with Load Cap Value ..... 10
Recommendation for ECO ..................................... 11
Crystal Analysis for WCO ....................................... 11
8.1
Frequency Variation with Temperature .......... 11
8.2
Start-Up Time and ESR ................................. 12
8.3
Load Capacitance .......................................... 12
8.4
CL and Clock Accuracy ................................. 13
8.5
Frequency Variation Across Boards .............. 13
9
Recommendations for WCO................................... 14
10 Layout Considerations for PCB .............................. 14
11 Summary ................................................................ 15
12 References ............................................................. 15
13 Appendix: Frequency Error
(Transmit Center Frequency Tolerance) ................ 17
Worldwide Sales and Design Support ............................. 19
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8
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4
5
6
1
Introduction
This application note helps you select the ECO crystal and the WCO crystal for PSoC 4/PRoC BLE devices and tune
them for optimum performance.
Bluetooth Low Energy (BLE) is a timing-sensitive technology in which an inaccurate ECO clock can degrade the
physical layer RF performance; similarly, an inaccurate WCO clock can lead to increased power consumption in a
peripheral.
The on-chip ECO circuit with an external crystal is used to synthesize a 24-MHz clock to run the BLE subsystem. The
clock sets the protocol timing for link-layer operations and derives the carrier frequency for physical-layer RF circuits.
An external WCO crystal is used to derive the 32.768-kHz clock that maintains link-layer timing synchronization when
the BLE subsystem is in a low-power mode.
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Document No. 001-95089 Rev. *A
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PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
2
2.1
Crystal Oscillator Basics
Crystal Oscillator Circuitry
A typical crystal oscillator circuit is shown in
Figure 1.
The oscillator circuit has one inverting amplifier, one feedback
resistor (R), two capacitors (C
1
and C
2
), and a quartz crystal (XTAL)
Figure 1. Basic Crystal Oscillator Circuit
Inverting Amplifier
R
XI
XO
XTAL
C
1
C
2
During normal operation, the crystal and the capacitors form a π-network band-pass filter that provides a 180-degree
phase shift and a voltage gain from the output to input at approximately the resonant frequency of the crystal.
The resistor R acts as a feedback resistance, biasing the inverter in its linear region of operation and effectively
causing it to function as a high-gain inverting amplifier.
The combination of the 180-degree phase shift from the π- network and the negative gain from the inverter results in
a positive loop-gain (positive feedback), making the bias point set by the feedback resistor unstable and leading to
oscillation.
2.2
Load Cap Value (C
L
)
The load capacitance is the total capacitance seen by the crystal looking into the rest of the circuit (see
Figure 2).
Figure 2. Load Capacitance
Inverting Amplifier
R
XI
XO
C
L
XTAL
The correct operation of a crystal oscillator circuit depends on the value of the total load capacitance value C
L
that is
composed of not only the two capacitors C
1
and C
2
, but also the parasitic capacitances and pin capacitances.
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Document No. 001-95089 Rev. *A
2
PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
Figure 3. Total Load Capacitance Including Parasitic Capacitance and Pin Capacitance
Inverting Amplifier
R
XI
XO
XTAL
C
PIN1
C
PCB1
C
1
C
2
C
PCB2
C
PIN2
C
T1
= C
1
+ C
PCB1
+ C
PIN1
C
T2
= C
2
+ C
PCB2
+ C
PIN2
Equation 1:
Where,
C
1,
C
2
= Node Capacitance at XI and XO
C
T1
, C
T2 =
Total node capacitance (including pin capacitance and parasitic capacitance)
C
PCB1 ,
C
PCB2
= Parasitic Capacitance between PCB pads of the crystal
C
PIN1,
C
PIN2
= Input capacitance of the oscillator pins
C
L
= Total load capacitance seen by the crystal
The load capacitance required to generate an accurate crystal frequency is specified in the crystal datasheet.
Capacitors C
1
and C
2
in
Figure 1
should be chosen such that the value of C
L
from
Equation 1
matches the datasheet
value. The oscillator of PSoC4/PRoC BLE devices is designed to work with an 8-pF load capacitance, which requires
that the chosen crystal has 8-pF load capacitance.
The crystal will not oscillate at the frequency specified in the crystal datasheet if the passive crystal load circuitry does
not provide the load capacitance (C
L
) that is required for the crystal. Too low a capacitive load will result in a crystal
oscillator frequency higher than the specified value, while too high a capacitive load will result in a lower oscillation
frequency. This frequency offset will be directly translated to an offset in the RF carrier frequency and symbol timing
accuracy of the device.
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Document No. 001-95089 Rev. *A
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PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
2.3
Crystal Equivalent RLC Circuit
Figure 4
shows the equivalent RLC circuit of the crystal.
Figure 4. Equivalent RLC Circuit of the Crystal
Inverting Amplifier
R
XI
C
L
XO
C
0
L
M
C
M
R
M
Where,
R
M
= Motional resistance of the crystal
C
0
= Shunt capacitance
C
L
= Load capacitance
C
M
= Motional capacitance
L
M
= Motional inductance
This circuit represents parallel resonant mode. The frequency of oscillation is derived from
Equation 2:
Equation 2:
Where
2.3.1
is the series resonant frequency of the oscillator and
is the frequency of oscillation.
E q u i va l e n t S e r i e s R e s i s t a n c e ( E S R )
This resistance represents the resistive element of the quartz crystal equivalent circuit. It is the equivalent impedance
of the crystal at its natural resonant frequency (series resonance). The gain of the oscillator amplifier directly depends
on the ESR: the higher the ESR value, the higher will be the gain required by the oscillator amplifier to oscillate at the
desired frequency.
Internal oscillator circuits in every chip are designed to work with a maximum specified value of ESR such that the
biasing point of the amplifier becomes unstable, resulting in oscillations.
The ESR for a crystal is given by the following equation:
Equation 3:
See the crystal datasheet for the ESR value. Its value depends on the crystal frequency and usually varies from 20 Ω
to 100 Ω.
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Document No. 001-95089 Rev. *A
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PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
2.4
Drive Level
This is a measure of the amount of power dissipated (in µW) across the crystal. The maximum drive level is the
maximum power a crystal can dissipate while still maintaining the specified performance. A high drive-level causes
problems such as instability and aging. The drive level should be considered in your design to avoid premature aging
and damage to the crystal. You should choose a crystal whose drive level specification meets your design drive level
requirement.
2.5
PPM Error
The crystal clock accuracy is usually defined in parts per million (ppm), which means the inaccuracy in the number of
6
clock cycles measured per 10 (1 million) clock cycles.
Equation 4:
For example, if a 24-MHz crystal oscillator provides a clock of 23.999928 MHz, then the clock accuracy is -72/24 = -3
ppm
There are many reasons for ppm variation. Some of these are discussed below:
Initial Tolerance (ppm):
The deviation from the nominal crystal frequency for different devices under identical
conditions (temperature, PCB layout, voltage, etc). This is a datasheet parameter.
Temperature Drift (ppm):
The deviation from the nominal crystal frequency over temperature.
Aging (ppm/year):
The cumulative change in the frequency of oscillation experienced by a crystal over a year. The
variation due to aging may be different in different years. This may be +/- 1 ppm for the first year and +/- 20 ppm after
15 years.
Pullability:
This is the change in crystal oscillator frequency due to a change in the load capacitance. It is typically
20 ppm/pF. The parasitic load capacitance varies between 2.5 to 3.5 pF, which can cause the ppm to shift outside the
BLE specification limit of +/-50 ppm. Therefore, the board parasitic capacitance should also be considered while
choosing the load capacitor value for the crystal.
Parasitic Capacitance:
Stray capacitances from the PCB and pin input add to the overall parasitic capacitance seen
by the crystal. This parasitic capacitance changes the load capacitance value.
3
Effects of Inaccurate ECO Crystal Frequency on RF Performance
The data transmitted over BLE has a symbol rate of 1 mega-symbol per second (symbol timing of 1 µs), where a
symbol refers to one bit of baseband signal that modulates the carrier. The symbol timing accuracy should be better
than ± 50 ppm. In addition, the deviation in the RF center frequency during a packet transmission should not exceed
± 150 kHz (See
Appendix: Frequency Error (Transmit Center Frequency Tolerance)).The
symbol timing and the
centre frequency are both derived from the 24-MHz crystal oscillator. Therefore, you should use a crystal that meets
the BLE specification because the deviation in the crystal oscillator clock directly impacts the RF performance.
A higher RF center-frequency deviation of the transmitter increases transmission leakages in adjacent channels that
result in the following:
Higher interference for receivers in adjacent channels
Possibility of not meeting the radio specifications
Increase in the spurious spillover in the adjacent channel that could result in failures in a band-edge test
A higher frequency-deviation of the receiver with respect to the transmitter could cause a part of the received energy
to fall outside the bandwidth of the baseband filter. This causes valid signal energy to be lost in the filter and results in
a reduced sensitivity (and hence a reduced range).
For GFSK receivers, the frequency deviation also causes a DC shift in the demodulated output and could result in the
decoded symbols to be erroneous This results in a higher PER (packet error rate) and reduced sensitivity.
Apart from these, a higher frequency-deviation of the receiver makes the receiver move closer to the adjacent
channel. Consequently, signals in adjacent channels impact the reception, thus reducing the selectivity.
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Document No. 001-95089 Rev. *A
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