The UT54ACS164E and the UT54ACTS164E are 8-bit shift
registers which feature AND-gated serial inputs and an asyn-
chronous clear. The gated serial inputs (A and B) permit com-
plete control over incoming data. A low at either input inhibits
entry of new data and resets the first flip-flop to the low level
at the next clock pulse. A high-level at both serial inputs sets
the first flip-flop to the high level at the next clock pulse. Data
at the serial inputs may be changed while the clock is high or
low, providing the minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition of the clock
input.
The devices are characterized over full HiRel temperature range
of -55°C to +125°C.
Notes:
1. Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
or Q
H
, respectively, before the indicated
steady-state input conditions were established.
2. Q
An
and Q
Gn
= the level of Q
A
or Q
G
before the most recent
↑
transition of
the clock; indicates a one-bit shift.
LOGIC SYMBOL
(9)
CLR
(8)
CLK
SRG8
R
C1/
&
1D
(3)
(4)
PINOUT
14-Lead Flatpack
Top View
A
B
Q
A
Q
B
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
Q
H
Q
G
Q
F
Q
E
CLR
CLK
A
B
(1)
(2)
Q
A
Q
B
(5)
Q
(6)
C
Q
D
(10)
Q
(11)
E
Q
(12)
F
Q
(13)
G
Q
H
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1
LOGIC DIAGRAM
(9)
(8)
C
R
K
S
C
R
K
S
(3)
Q
A
Q
B
C
R
K
S
(4)
Q
C
C
R
K
S
(5)
Q
D
C
R
K
S
(6)
Q
E
C
R
K
S
(10)
Q
F
C
R
K
S
(11)
Q
G
C
R
K
S
(12)
Q
H
(13)
CLR
CLK
SERIAL
(1)
A
B (2)
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+ .3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
2
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS164E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55°C < T
C
< +125°C)
SYMBOL
V
IL
Description
Low-level input voltage
1
High-level input voltage
1
CONDITION
VDD
3.0V
5.5V
V
IH
3.0V
5.5V
I
IN
V
OL
Input leakage current
Low-level output voltage
3
High-level output voltage
3
Short-circuit output current
2 ,4
V
IN
= V
DD
or V
SS
I
OL
= 100μA
5.5V
3.0V
4.5V
V
OH
I
OH
= -100μA
3.0V
4.5V
I
OS
V
O
= V
DD
and V
SS
3.0V
5.5V
I
OL
Low level output current
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
I
OH
High level output current
9
V
IN
= V
DD
or V
SS
V
OH
= VDD-0.4V
P
total
I
DDQ
C
IN
C
OUT
Power dissipation
2, 8
Quiescent Supply Current
Input capacitance
5
Output capacitance
5
C
L
= 50pF
V
IN
= V
DD
or V
SS
ƒ
= 1MHz
ƒ
= 1MHz
3.0V
5.5V
3.0V
5.5V
5.5V
3.0V
5.5V
0V
0V
2.75
4.25
-100
-200
6
8
-6
-8
1.9
0.76
10
15
15
mW/
MHz
μA
pF
pF
mA
100
200
mA
mA
2.1
3.85
-1
1
0.25
0.25
V
μA
V
MIN
MAX
0.9
1.65
V
UNIT
V
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B.
8. Power dissipation specified per switching output.
9. This value is guaranteed based on characterization data, but not tested.
3
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS164E
2
(V
DD
= 3.0V to 5.5V; V
SS
= 0V
1
, -55°C < T
C
< +125°C)
SYMBOL
t
PHL1
PARAMETER
CLK to Qn
CONDITION
C
L
= 30pF
V
DD
3.0V & 3.6V
4.5V & 5.5V
C
L
= 50pF
3.0V & 3.6V
4.5V & 5.5V
t
PLH1
CLK to Qn
C
L
= 30pF
3.0V & 3.6V
4.5V & 5.5V
C
L
= 50pF
3.0V & 3.6V
4.5V & 5.5V
t
PLH2
CLR to Qn
C
L
= 30pF
3.0V & 3.6V
4.5V & 5.5V
C
L
= 50pF
3.0V & 3.6V
4.5V & 5.5V
f
MAX
t
SU1
t
SU2
t
H3
t
W
Maximum clock frequency
Data setup time before CLK↑
CLR inactive
Setup time before CLK
↑
Data hold time after CLK
↑
Minimum pulse width
CLR low
CLK high
CLK low
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
3.0V, 4.5V, and
5.5V
3.0V, 4.5V, and
5.5V
3.0V, 4.5V, and
5.5V
3.0V, 4.5V, and
5.5V
3.0V, 4.5V, and
5.5V
4
4
2
6
MINIMUM
4
4
4
4
2
2
2
2
5
5
5
5
MAXIMUM
21
17
25
21
18
14
22
18
21
17
25
21
83
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose
≤
1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
3. Based on characterization, hold time (t
H
) of 0ns can be assumed if data setup time (t
SU1
) is >10ns. This is guaranteed, but not tested.
4
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS164E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55°C < T
C
< +125°C)
SYMBOL
V
IL
Description
Low-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
V
IN
= V
DD
or V
SS
I
OL
= 6mA
I
OL
= 8mA
V
OH
High-level output voltage
3
I
OH
= -6mA
I
OH
= -8mA
I
OS
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
CONDITION
VDD
3.0V
5.5V
V
IH
3.0V
5.5V
I
IN
V
OL
5.5V
3.0V
4.5V
3.0V
4.5V
3.0V
5.5V
I
OL
Low level output current
10
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
I
OH
High level output current
10
V
IN
= V
DD
or V
SS
V
OH
= VDD-0.4V
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, ,9
Quiescent Supply Current
Quiescent Supply Current Delta
C
L
= 50pF
V
IN
= V
DD
or V
SS
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz
ƒ
= 1MHz
0V
0V
15
15
pF
pF
3.0V
5.5V
3.0V
5.5V
5.5V
3.0V
5.5V
5.5V
2.4
3.15
-100
-200
6
8
-6
-8
1.9
0.76
10
1.6
mW/
MHz
μA
mA
mA
100
200
mA
2.0
2.75
-1
1
0.4
0.4
μA
V
V
V
V
mA
MIN
MAX
0.8
0.8
V
UNIT
V
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
8. Power does not include power contribution of any TTL output sink current
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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