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Datasheet> 器件分类 > 存储> 存储> IDT71V2548S150BGI8
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IDT71V2548S150BGI8

产品描述ZBT SRAM, 256KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
产品类别存储    存储   
文件大小487KB，共26页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

IDT71V2548S150BGI8概述

ZBT SRAM, 256KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71V2548S150BGI8规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码BGA
包装说明14 X 22 MM, PLASTIC, BGA-119
针数119
Reach Compliance Codenot_compliant
ECCN代码3A991.B.2.A
最长访问时间3.8 ns
其他特性PIPELINED ARCHITECTURE
JESD-30 代码R-PBGA-B119
JESD-609代码e0
长度22 mm
内存密度4718592 bit
内存集成电路类型ZBT SRAM
内存宽度18
湿度敏感等级3
功能数量1
端子数量119
字数262144 words
字数代码256000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织256KX18
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装形状RECTANGULAR
封装形式GRID ARRAY
并行/串行PARALLEL
峰值回流温度（摄氏度）260
认证状态Not Qualified
座面最大高度2.36 mm
最大供电电压 (Vsup)3.465 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn63Pb37)
端子形式BALL
端子节距1.27 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间30
宽度14 mm

IDT71V2548S150BGI8文档预览

128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
x
x
IDT71V2546
IDT71V2548
Features
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546/48 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546/48 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546/48 has an on-chip burst counter. In the burst mode,
the IDT71V2546/48 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
x
x
x
x
x
x
x
x
x
x
Description
The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
TM
, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one clock
Pin Description Summary
A
0
-A
17
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
5294 tbl 01
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
OCTOBER 2000
DSC-5294/02
1
©2000 Integrated Device Technology, Inc.
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
-A
17
ADV/LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK, ADV/LD low,
CEN
low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/
LD
is sampled hig h then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous
inputs, including clock are ignored and outputs re main unchanged. The effect of
CEN
sampled high on the device outputs is as if the low to hig h clock transition did not occur.
For normal operation,
CEN
must be sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW
1
-BW
4
) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later.
BW
1
-BW
4
can all be tied low if
always doing write to the entire 36-bit word.
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the
IDT71V2546/48. (CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the
rising edge of clock, initiates a deselect cycle. The ZBT
TM
has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip.
CE
2
has inverted po larity but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71V2546/48. Except for
OE,
all timing references for the
device are made with respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
Burst order selection input. When
LBO
is high the Interleaved burst sequence is selected.
When
LBO
is low the Linear burst sequence is selected.
LBO
is a static input and it must
not change during device operation.
Asynchronous output enable.
OE
must be low to read data from the 71V2546/48. When
OE
is high the I/O pins are in a high-impedance state.
OE
does not need to be actively
controlled for read and write cycles. In normal operation,
OE
can be tied low.
3.3V core power supply.
2.5V I/O Supply.
Ground.
5294 tbl 02
R/W
Read / Write
I
N/A
CEN
Clock Enable
I
LOW
BW
1
-BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
Chip Enable
Clock
Data Input/Output
Linear Burst Order
I
I
I/O
I
HIGH
N/A
N/A
LOW
OE
Output Enable
I
LOW
V
DD
V
DDQ
V
SS
NOTE:
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
Address A [0:16]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
128Kx36 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5294 drw 01a
,
Data I/O [0:31],
I/O P[1:4]
6.42
3
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
Address A [0:17]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
256x18 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5294 drw 01b
Data I/O [0:15],
I/O P[1:2]
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
2.375
0
1.7
1.7
-0.3
(1)
Typ.
3.3
2.5
0
____
____
____
Max.
3.465
2.625
0
V
DD
+0.3
V
DDQ
+0.3
(2)
0.7
Unit
V
V
V
V
V
V
5294 tbl 03
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC
/2, once per cycle.
6.42
4
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
(1)
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
V
DDQ
2.5V±5%
2.5V±5%
5294 tbl 05
NOTE:
1. T
A
is the "instant on" case temperature.
Pin Configuration — 128K x 36
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
A
6
A
7
CE
1
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
DD
(1)
V
DD
V
DD
(1)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5294 drw 02
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
(1)
V
DD
V
SS
(4)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
,
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. DNU = Do not use; Pins 38, 39, 42, and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK on future
revisions. Within this current version, these pins are not connected.
4. Pin 64 does not have to be connected directly to V
SS
as long as the input voltage is
≤
V
IL
. On future revisions pin 64
will be used for ZZ (sleep mode).
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
A
10
A
11
A
12
A
13
A
14
A
15
A
16
6.42
5
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