NCP121
150 mA, High Accuracy,
Very Low Dropout Bias Rail
CMOS Voltage Regulator
The NCP121 is a high accuracy 150 mA VLDO equipped with
NMOS pass transistor and a separate bias supply voltage (V
BIAS
). The
device provides stable, very accurate output voltage with low noise
suitable for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
NCP121 features low I
Q
consumption. The XDFN6 1.2 mm x 1.2 mm
package is optimized for use in space constrained applications.
Features
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MARKING
DIAGRAM
XDFN6
CASE 711AT
XX M
T
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 0.8 V to 5.5 V
Bias Voltage Range: 2.4 V to 5.5 V
Fixed Output Voltage Device
Output Voltage Range: 0.8 V to 2.1 V
±1.0%
Accuracy over Line, Load and Temperature, 0.2% V
OUT
@
25°C
Ultra−Low Dropout: 75 mV Maximum at 150 mA
Very Low Bias Input Current of Typ. 80
mA
Very Low Bias Input Current in Disable Mode: Typ. 0.5
mA
Logic Level Enable Input for ON/OFF control
Output Active Discharge Option available
Stable with a 1
mF
Ceramic Capacitor
Available in XDFN6 − 1.2 mm x 1.2 mm x 0.4 mm package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
XX = Specific Device Code
M = Date Code
PIN CONNECTIONS
OUT
IN
1
6
NC
2
Thermal
Pad
5
GND
EN
3
4
BIAS
(Top VIew)
Typical Applications
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 7 of this data sheet.
•
Battery−powered Equipment
•
Smartphones, Tablets
•
Cameras, DVRs, STB and Camcorders
V
BIAS
2.7 V
NCP121
100 nF
BIAS
V
IN
1.2 V
IN
1
mF
EN
GND
OUT
1
mF
V
OUT
1.05 V @ 150 mA
V
EN
Figure 1. Typical Application Schematics
©
Semiconductor Components Industries, LLC, 2015
1
October, 2015 − Rev. 1
Publication Order Number:
NCP121/D
NCP121
IN
EN
ENABLE
BLOCK
UVLO
CURRENT
LIMIT
OUT
BIAS
150
W
VOLTAGE
REFERENCE
+
−
THERMAL
LIMIT
*Active
DISCHARGE
GND
*Active output discharge function is present only in NCP121AMXyyyTCG devices.
yyy denotes the particular output voltage option.
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
Pad
Pin Name
OUT
N/C
EN
BIAS
GND
IN
Regulated Output Voltage pin
Not internally connected
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode.
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage Lockout Circuit.
Ground pin
Input Voltage Supply pin
Should be soldered to the ground plane for increased thermal performance.
Description
ABSOLUTE MAXIMUM RATINGS
Rating
Input Voltage (Note 1)
Output Voltage
Chip Enable and Bias Input
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Symbol
V
IN
V
OUT
V
EN,
V
BIAS
t
SC
T
J
T
STG
ESD
HBM
ESD
MM
Value
−0.3 to 6
−0.3 to (V
IN
+0.3)
≤
6
−0.3 to 6
unlimited
150
−55 to 150
2000
200
Unit
V
V
V
s
°C
°C
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, XDFN6 1.2 mm x 1.2 mm Thermal Resistance, Junction−to−Air
Symbol
R
qJA
Value
170
Unit
°C/W
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2
NCP121
ELECTRICAL CHARACTERISTICS
−40°C
≤
T
J
≤
85°C; V
BIAS
= 2.7 V or (V
OUT
+ 1.6 V), whichever is greater, V
IN
= V
OUT(NOM)
+ 0.3 V, I
OUT
= 1 mA, V
EN
= 1 V, unless
otherwise noted. C
IN
= 1
mF,
C
BIAS
= 0.1
mF,
C
OUT
= 1
mF
(effective capacitance) (Note 3). Typical values are at T
J
= +25°C. Min/Max
values are for −40°C
≤
T
J
≤
85°C unless otherwise noted. (Note 4)
Parameter
Operating Input
Voltage Range
Operating Bias Voltage
Range
Undervoltage Lock−out V
BIAS
Rising
Hysteresis
Output Voltage
Accuracy
Output Voltage
Accuracy
V
IN
Line Regulation
V
BIAS
Line Regulation
Load Regulation
V
IN
Dropout Voltage
V
BIAS
Dropout Voltage
Output Current Limit
Bias Pin Operating
Current
Bias Pin Disable
Current
Vinput Pin Disable
Current
EN Pin Threshold
Voltage
EN Pull Down Current
Turn−On Time
Power Supply
Rejection Ratio
V
OUT(NOM)
+ 0.3 V
≤
V
IN
≤
5.0 V
2.7 V or (V
OUT(NOM)
+ 1.6 V), whichever is
greater < V
BIAS <
5.5 V
I
OUT
= 1 mA to 150 mA
I
OUT
= 150 mA (Note 5)
I
OUT
= 150 mA, V
IN
= V
BIAS
(Note 5)
V
OUT
= 90% V
OUT(NOM)
V
BIAS
= 2.7 V
V
EN
≤
0.4 V
V
EN
≤
0.4 V
EN Input Voltage “H”
EN Input Voltage “L”
V
EN
= 5.5 V
C
OUT
= 1
mF,
From assertion of V
EN
to
V
OUT
= 98% V
OUT(NOM)
, V
OUT(NOM) =
1.05 V
V
IN
to V
OUT
, f = 1 kHz, I
OUT
= 150 mA,
V
IN
≥
V
OUT
+0.5 V
V
BIAS
to V
OUT
, f = 1 kHz, I
OUT
= 150 mA,
V
IN
≥
V
OUT
+0.5 V
Output Noise Voltage
Thermal Shutdown
Threshold
Output Discharge
Pull−Down
V
IN
= V
OUT
+0.5 V, V
OUT(NOM)
= 1.05 V,
f = 10 Hz to 100 kHz
Temperature increasing
Temperature decreasing
V
EN
≤
0.4 V, V
OUT
= 0.5 V,
NCP121A options only
R
DISCH
−40°C
≤
T
J
≤
85°C, V
OUT(NOM)
+ 0.3 V
≤
V
IN
≤
5.0 V, 2.7 V or (V
OUT(NOM)
+ 1.6 V), whichever is
greater < V
BIAS
< 5.5 V, 1 mA < I
OUT
< 150 mA
Test Conditions
Symbol
V
IN
V
BIAS
UVLO
V
OUT
−1.0
Min
V
OUT
+V
DO
(V
OUT
+1.35)
≥2.4
1.6
0.2
+1.0
Typ
Max
5.5
5.5
Unit
V
V
V
%
V
OUT
Line
Reg
Line
Reg
Load
Reg
V
DO
V
DO
I
CL
I
BIAS
I
BIAS(DIS)
I
VIN(DIS)
V
EN(H)
V
EN(L)
I
EN
t
ON
PSRR(V
IN
)
PSRR(V
BIAS
)
V
N
0.9
200
±0.2
0.01
0.01
1.5
37
1.1
330
80
0.5
0.5
75
1.4
600
110
1
1
%
%/V
%/V
mV
mV
V
mA
mA
mA
mA
V
0.4
0.3
150
70
80
40
160
140
150
1.0
mA
ms
dB
dB
mV
RMS
°C
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T
A
= 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when V
OUT
falls 3% below V
OUT(NOM)
.
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3
NCP121
APPLICATIONS INFORMATION
2.6 V − 4.2 V
.
VBAT
NCP121
DC/DC
1.2 V V
OUT(NOM)
IN
EN
Processor
I/O
I/O
To other circuits
GND
LX
FB
1.2 V
EN
BIAS
IN
GND
OUT
1.05 V
LOAD
Figure 3. Typical Application: Low−Voltage Post−Regulator with ON/OFF functionality
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4
NCP121
TYPICAL CHARACTERISTICS
At T
J
= +25°C, V
IN
= V
OUT(TYP)
+ 0.3 V, V
BIAS
= 2.7 V, V
EN
= V
BIAS
, V
OUT(NOM)
= 1.05 V, I
OUT
= 150 mA,
C
IN
= 1
mF,
C
BIAS
= 0.1
mF,
and C
OUT
= 1
mF
(effective capacitance), unless otherwise noted.
V
DO
(V
IN
− V
OUT
) DROPOUT VOLTAGE (mV)
60
50
+125°C
40
+85°C
30
20
10
0
0
50
100
150
I
OUT
, OUTPUT CURRENT (mA)
+25°C
−40°C
200
180
160
140
120
100
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
BIAS
− V
OUT
(V)
+125°C
+85°C
+25°C
I
OUT
= 150 mA
V
DO
(V
IN
− V
OUT
) DROPOUT VOLTAGE (mV)
−40°C
Figure 4. V
IN
Dropout Voltage vs. I
OUT
and
Temperature T
J
V
DO
(V
BIAS
− V
OUT
) DROPOUT VOLTAGE (mV)
1400
1300
1200
I
BIAS
(mA)
1100
1000
900
800
0
50
100
150
I
OUT
, OUTPUT CURRENT (mA)
+85°C
+125°C
40
20
0
0
−40°C
+25°C
140
120
Figure 5. V
IN
Dropout Voltage vs. (V
BIAS
−
V
OUT
) and Temperature T
J
+85°C
100
80
60
−40°C
+25°C
+125°C
50
100
150
I
OUT
, OUTPUT CURRENT (mA)
Figure 6. V
BIAS
Dropout Voltage vs. I
OUT
and
Temperature T
J
200
180
160
140
I
BIAS
(mA)
120
100
80
60
40
20
0
2.0
−40°C
+25°C
+85°C
+125°C
I
CL
, CURRENT LIMIT (mA)
500
600
Figure 7. BIAS Pin Current vs. I
OUT
and
Temperature T
J
+85°C
400
300
+25°C
200
100
0
+125°C
−40°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
BIAS
(V)
V
BIAS
− V
OUT
(V)
Figure 8. BIAS Pin Current vs. V
BIAS
and
Temperature T
J
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5
Figure 9. Current Limit vs. (V
BIAS
− V
OUT
)
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